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\begin{center}
{\Large CS/ECE 347, Spring 1996}\\[1ex]
{\Large Recitation Assignment 8: Cache basics}\\[1ex]
{\large Assigned: Thu., Apr.~5\\Due: Mon., Apr.~8}
\end{center}

\section{Problem 1}
Consider an address space of $128$ byte-addresses and a cache with 32
total data bytes and a line size of $4$ bytes. Complete the following
table for the different kinds of cache organizations:

\begin{center}
\begin{tabular}{|l||c|c|c|c|}
\hline
& direct mapped & 2-way set assoc & 4-way set assoc & fully assoc \\
\hline
\hline
&&&&\\
n (\# address bits)&&&&\\
&&&&\\
\hline
&&&&\\
t (\# tag bits)&&&&\\
&&&&\\
\hline
&&&&\\
s (\# set index bits)&&&&\\
&&&&\\
\hline
&&&&\\
b (\# block offset bits)&&&&\\
&&&&\\
\hline
&&&&\\
S (\# sets) &&&&\\
&&&&\\
\hline
&&&&\\
E (\# entries/set) &&&&\\
&&&&\\
\hline
\end{tabular}
\end{center}

\section{Problem 2}
Assume the address space, cache size, and line size from Problem 1.
For each of the following addresses, indicate (1) the set number that
the address is mapped to in the cache and (2) the corresponding tag
bits.
\begin{center}
\begin{tabular}{|l||c|c|c|c|c|c|c|c|}
\hline
 & \multicolumn{2}{c}{direct mapped} 
 & \multicolumn{2}{c}{2-way set assoc} 
 & \multicolumn{2}{c}{4-way set assoc} 
 & \multicolumn{2}{c}{fully assoc} \\
\hline
address& \ \ set\ \  & tag bits & \ \ set\ \  & tag bits &\ \ set\ \  
& tag bits & \ \ set\ \  & tag bits\\
\hline
\hline
&&&&&&&&\\
25&&&&&&&&\\
&&&&&&&&\\
\hline
&&&&&&&&\\
75&&&&&&&&\\
&&&&&&&&\\
\hline
&&&&&&&&\\
90&&&&&&&&\\
&&&&&&&&\\
\hline
\end{tabular}
\end{center}
\end{document}
