15-740 Fall '95
Notes on Assignments

The term LIB740 refers to the library file HOME740/lib/lib740.a, containing the object code for any runtime support routines supplied for your use. For your convenience, the sources for the library are available in subdirectory HOME740/src.

The following information is in reverse order of assignment, i.e., the most recent assignments appear first.

Assignment 6

Platforms

Performance Issues

• You can diddle some of the run time flags. These are documented in the man page for smv, found in HOME740/public/man/man1. Here is a postscript version. Useful flags are -c, -k, and -r.
• You can temporarily replace one of the caches with a ``fake cache'' to reduce the size of the state space. Here's an example SMV description of such a model. You can do most of your debugging and counterexample generation using this reduced model, and then run a full 3 cache version when you're certain everything should work.
• On each run, strip away any verification conditions and any fairness constraints that aren't relevant to the particular task.

Task 1: Generating Interesting Behavior

Task 3: Implementing LL and SC

Here are some clarifications

• You do not need to model the data handling part of these operations, just the control. Note that you don't need to actually model the lock acquisition code shown in the assignment in SMV.
• Instead of adding another Boolean signal between cache and processor, you may want to generalize the stall signal to a three-valued status signal, with values stall, succeed, and fail
• Note that the MIPS instruction set puts very few restrictions on the use of LL and SC. Although these instructions are typically used in a very stylized way, you should not assume a particular usage pattern in your implementation. In particular:
  • There is nothing special about the memory locations referenced by LL and and SC. They can be used for normal loads and stores.
  • The link register will not be disturbed if the connected processor does a read, write, or store conditional operation on the memory location. It will also not be disturbed if some other processor reads the location. It will be cleared only if some other processor writes (or performs a store-conditional operation on) the memory location.
• You must constrain your processor model so that it will never attempt an operation for which the behavior is unspecified. [In general, the environment model should never do anything invalid to the system].
• Note that the cache may lose its copy of a block between the LL and SC yet still succeed. You'll need to carefully work out the updating of the link register.

Here is some advice:

• Extend the state diagram to include the handling of LL and SC operations by the processor, as well as the effects different bus operations can have on the link register.
• Be sure you consider all possible states, and all possible relations between the addresses specified by the processor, the cache tag, and the bus address.
• Try to make a failing SC behave as much as possible like a no-op, i.e., not causing bus traffic or a change in cache state.
• Be sure to document your design well in your writeup. The problem is challenging, but it's fun to work through all the details.

Assignment 5

Assignment 4

Assignment 3

• For Task 1.A, the question has been changed. I gave you the answer of the sign extension method. Now, your task is to justify why this method works. Here is the modified assignment in postscript form.
• In Task 1.B, you should write a parameterized multiplier such that you can fully test your multiplier by resizing it to a 8x8 multiplier and verifying it with all of the possible input combinations. File asst3/m_8x8.test is the test cases for a 8x8 multiplier.

Assignment 2

I've made changes in the files Makefile, mips.h, and mips_sim.c:

• Makefile: Fixed to allow generation of a .O file from a .c file according to suggestions by Rob Miller. You should use "gmake" instead of "make", though.
• mips.h: Old version stored as mips.v1.h. Fixed error in macro GET_I26.
• mips_sim.c: Old version stored as mips_sim.v1.c. Fixed to handle BREAK instruction during EX phase rather than ID. This will make it possible for you to fetch & decode a BREAK instruction following a branch that later gets cancelled. The *right* way to handle this instruction would be to move the exception condition through pipe registers as discussed in class yesterday. For the purpose of this assignment, what I've done is good enough.
• mips_sim.c: Set so that BREAK causes stall in EX stage. Old version in mips_sim.v2.c
• In addition, I've added files jtest.{c,O,answer} giving some tests for jump instructions. Not a comprehensive test set, but reasonably stressful!

Assignment 1

If you are using the machine which word size is 64 bits, e.g. Alpha, you can use m100_w64.test file under HOME740/asst/asst1 directory.