Verilog Simulation Instructions

At the unix prompt in your working directory, type: verilog harness.v mult1.v

The simulations should succeed. Harness runs for 500 cycles until it decides that it has tested the multiplier enough. The simulation generates a database of waveforms in waves.shm. You can view this database on any platform, and for any input language using the simwaves program:

simwave&

When the window comes up, do:

  1. File/Database/Load...
    2. And select the waves directory, and hit OK.
  2. Edit/Add Signals...
    3. This is a hierarchical signal name browser. Find and add: a, b, c, valid, and clock.
  3. View/Zoom Out
    4. Do this a couple of times so that you can see at least ten cycles. Make sure that the left side of the display shows time == 0. The first rising edge of valid must be visible.
  4. File/Print/Single Page...
    5. Generate a PostScript file of the current view. Print this out and turn it in.
  5. File/Exit

Helpful Hints (in case Verilog doesn't run):

  1. If you can't get a license read this.

    2.  
  2. If veriilog won't start because shared  libraries are missing, you should create a directory, /tmp/shared, and insert soft links (ln -s) from the names verilog wants to use to the latest version on your system, then add /tmp/shared to you LD_LIBRARY_PATH.