Copy the following into your working directory:
.synopsys_dc.setup
% design_analyzer&
Choose File->Read....Select Mult1.v or Mult1.vhd and hit OK. A window should come up that describes the "Inferred memory devices in process." Hit Cancel to close this window. The main design analyzer window should now show a block named multiplier.
Select the multiplier block by clicking on it with the left mouse button. Push the down arrow icon on the left side of the screen. The view should now show all the inputs and outputs in the multiplier design.
Synopsys needs to know that all of the I/Os in this design should be pads on an single FPGA. Choose:Attributes->Optimization Directives->Design
and click "Port is Pad" to on. Hit Apply to commit these changes and Cancel to close the window.
Choose:Tools->FPGA Compiler...
and click "Insert Pads...". Hit OK in the "Insert Pads" dialog box. Leave the FPGA Compiler window up. You're going to need it.
Select the clk pin by clicking on it (an thereby highlighting it) in the Symbol View. Choose:Attributes->Clocks->Specify
Change the clock period to 250 ns. You can use any clock period you like, but 250 ns is guarenteed to work without too much effort or run-time. Synopsys actually generates its best designs when you give it difficult but reachable constraints. Hit Apply to commit these changes and Cancel to close the window.
In the FPGA Compiler Window, hit Optimization.... Hit OK to run the optimizer with the default settings.
In the FPGA Compiler Window, hit Report.... Select the Area and Timing report and hit Apply to run the report. You may want to save this report to a file. The area is broken down into Combinatorial and Noncombinatorial area. In both terms, the unit is CLBs.
You've got to convert the internal representation of CLBs into combinatorial gates. To do this, in the FPGA Compiler window, hit Cells to Gates.
In the FPGA Compiler window, hit Save As.... In this window, select XNF from the file format menu. Change the name to Mult1.sxnf, and hit OK.
Do File->Quit.
You need to run this program to convert the "Synopsys XNF", Mult1.sxnf, to proper Xilinx xnf. At the UNIX prompt, run:% syn2xnf -p 4013EHQ240 Mult1
This program should create a Mult1.xnf file from Mult1.sxnf.
The 4013EHQ240 is one part and package combination you can use. To see other parts, do syn2xnf -l. But remember that only 4000E family parts with speed grade of -3 are acceptable for comparison to other designs.