VHDL vs. Verilog: An ongoing religious war. I prefer Verilog.
Verilog dominates Silicon Valley industry, but VHDL wins with anybody who
does government work, people who like ADA, and Europeans. I typically wouldn't
ask people to work in VHDL, but it is the language used to describe all
the peripheral components of the Wild-One boards that we will be using
in the second lab. Therefore, it may behoove you to take the plunge and
learn VHDL now. There are complete online reference manuals for both languages,
as well as lots of good books. Another reason to use VHDL is that
we are expecting Altera boards which are easiest
to program using AHDL, an Altera variant of VHDL.
Synplicity vs. Synopsys: Synopsys is the industry standard, does everything synthesis tools should do. Synplicity was created as a reaction to the accumulated complexity of Synopsys. Synplicity is easy, but I've heard that its mapper and estimation tools aren't great.
XDM vs dsgnmgr: Xilinx's newest tools (dsgnmgr) have a much slicker GUI, and support all the new huge devices. XDM is a bit dated, but it works pretty well. On the old AIX tools, there also is the xmake program, which works like UNIX make. It knows all the programs you need to run to get from an netlist file to a placed and routed design. No GUI necessary.