Ali-Reza Adl-Tabatabai

http://www.cs.cmu.edu/~ali


CONTACT

Home Work
2125 Quinn Ave. Intel Corporation
Santa Clara, CA 95051 Microcomputer Research Labs
(408) 260-6866 2200 Mission College Blvd.
Santa Clara, CA 95052-8119
(408) 653-8053
ali@gomez.sc.intel.com

EDUCATION

1990 - 1996, Carnegie Mellon University, Pittsburgh, PA

School of Computer Science
Ph.D. in Computer Science, 1996
Thesis: Source-Level Debugging of Globally Optimized Code
Thesis Committee Members: Thomas Gross (chair), Peter Lee, Bernd Bruegge, Susan Graham (UC Berkeley)
M.S. in Computer Science, 1992

1984 - 1990, University of California, Los Angeles, CA

School of Engineering and Applied Sciences
B.S. in Computer Science and Engineering, 1990
Outstanding Bachelor of Science Award, UCLA School of Engineering and Applied Science, 1990


INDUSTRIAL EXPERIENCE

7/96 - present, Intel Corporation, Microcomputer Research Labs (MRL), Santa Clara, CA

Lead the design and implementation of a Just-In-Time Java compiler (JIT) for the Pentium Pro processor. Developed the C++ internal representation and the control-flow analysis phase of the next generation Intel processor architecture (Merced) research compiler. Represented Intel at the ICCD'96 panel session on "The Influence of Internet Applications on Microarchitecture".

11/94, Silicon Graphics, Inc., Mountain View, CA

Consulted the compiler and debugger development groups on source-level debugging of optimized code.

Summer 1991, MIPS Computer Corporation, Sunnyvale, CA

Extended the pixie binary translation system to handle the MIPS-III 64-bit instruction set extensions. Added new functionality to translate 64-bit MIPS-III binaries to 32-bit MIPS-I binaries.

Summer 1990, Advanced Micro Devices, Austin, TX

Tested and debugged the instruction issue and bus interface units for AM29030 RISC microprocessor. Designed solutions to logic errors and implemented solutions in production schematics.

1/89 - 9/89, Advanced Micro Devices, Austin, TX

Provided hardware and software technical support for the AM29000 RISC microprocessor family of products. Sofware products included compilers, assemblers, linkers, debuggers and simulators running on workstation and PC platforms. Hardware products included in-circuit emulators, target boards and PC-based plug-in cards.

Summer 1988, IBM Corporation, Rochester, MN

Tested workstation controller card and X.25 networking card for IBM AS/400 computers.


RESEARCH EXPERIENCE

1990 - 1996, Carnegie Mellon University, Pittsburgh, PA

Conducted research on the source-level debugging of globally optimized code. Developed and implemented new algorithms enabling source-level debugging of fully optimized code. Developed cmcc, a retargetable optimizing C compiler (written in C++) with code generators for MIPS, SPARC, iWarp and DLX. Designed cmcc's intermediate representation and C++ application frameworks for optimization and code generation. cmcc is currently being used for research on compiler engineering, advanced register allocation and instruction scheduling.

Contributed to the development and performance analysis of Omniware, a safe, efficient and language-independent system for executing mobile program modules. Contributed to the definition of the Omniware Virtual Machine. Implemented Omniware translator for the MIPS R4400 under IRIX.

Assisted Professor Dan Siewiorek in teaching the graduate "Wearable Computer Design" course. Managed team of graduate and undergraduate students in the design and implementation of software for Navigator, a wearable computer with a head-mounted display, speech input, and GPS, used for campus navigation. Ported the Sphinx speech recognition system onto the Navigator system.

1989 - 1990, UCLA Computer Science Department, Los Angeles, CA

Conducted research as an undergraduate research assistant on the feasibility of arithmetic algorithms in Application Specific Integrated Circuits. Developed a gate array implementation of an arithmetic module for performing division, square root and multiplication in a single shared data path.


PUBLICATIONS

Refereed Conference Publications

A. Adl-Tabatabai, T. Gross and G.Y. Lueh. Code Reuse in an Optimizing Compiler. In Proceedings of the ACM Conference on Object-Oriented Programming Systems, Languages, and Applications (OOPSLA'96), San Jose, CA, pages 51-68. ACM, October 1996.

A. Adl-Tabatabai and T. Gross. Source-Level Debugging of Scalar Optimized Code. In Proceedings of the ACM SIGPLAN Symposium on Programming Language Design and Implementation (PLDI'96), Philadelphia, PA, pages 33-43. ACM, May 1996.

A. Adl-Tabatabai, G. Langdale, S. Lucco and R. Wahbe. Efficient and Language-Independent Mobile Programs. In Proceedings of the ACM SIGPLAN Symposium on Programming Language Design and Implementation (PLDI'96), Philadelphia, PA, pages 127-136. ACM, May 1996.

A. Adl-Tabatabai and T. Gross. Detection and Recovery of Endangered Variables Caused by Instruction Scheduling. In Proceedings of the ACM SIGPLAN Symposium on Programming Language Design and Implementation (PLDI'93), Albuquerque, NM, pages 13-25. ACM, June 1993.

A. Adl-Tabatabai and T. Gross. Evicted Variables and the Interaction of Global Register Allocation and Symbolic Debugging. In Proceedings of the Twentieth ACM SIGPLAN Symposium on Principles of Programming Languages (POPL'93), Charleston, SC, pages 371-383. ACM, January 1993.

A. Adl-Tabatabai, T. Gross, G.Y. Lueh and J. Reinders. Modeling Instruction-Level Parallelism for Software Pipelining. In Proceedings of the IFIP WG10.3 Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Orlando, FL, pages 321-330. North Holland, January 1993.

Refereed Journal Publications

D. Siewiorek, A. Smailagic, J. Lee and A. Adl-Tabatabai. Interdisciplinary Concurrent Design Methodology as Applied to the Navigator Wearable Computer System. In Journal of Computer and Software Engineering, 2(3):259-292. 1994.

Other Publications

G.Y. Lueh, T. Gross. and A. Adl-Tabatabai. Global Register Allocation Based on Graph Fusion. In Ninth Workshop on Languages and Compilers for Parallel Computers , San Jose, CA. August, 1996. Also available as Technical Report CMU-CS-96-106, School of Computer Science, Carnegie Mellon University. February 1996.

A. Adl-Tabatabai and T. Gross. Engineering a Global Optimizer and Code Generator for Reuse. In Proceedings of the Fifth Workshop on Compilers for Parallel Computers, Malaga, Spain, pages 395-408. June 1995.

A. Adl-Tabatabai and T. Gross. Symbolic Debugging of Globally Optimized Code: Data Value Problems and Their Solutions. Technical Report CMU-CS-94-105, School of Computer Science, Carnegie Mellon University. January 1994.

A. Adl-Tabatabai and T. Gross. The Effects of Register Allocation and Instruction Scheduling on Symbolic Debugging. In Proceedings of the Supercomputer Debugging Workshop 1992, Dallas, TX, pages 115-127. October 1992.

A. Adl-Tabatabai. Nonresident and Endangered Variables: The Effects of Code Generation Optimizations on Symbolic Debugging. Technical Report CMU-CS-92-221, School of Computer Science, Carnegie Mellon University. December 1992.


PROFESSIONAL PRESENTATIONS

Conference and Workshop Talks

"The Influence of Internet Applications on Microarchitectures", IEEE International Conference on Computer Design, Austin, TX, October 1996.

"Code Reuse in an Optimizing Compiler,", ACM Conference on Object-Oriented Programming Systems, Languages, and Applications, San Jose, CA, October 1996.

"Engineering a Global Optimizer and Code Generator for Reuse," Fifth Workshop on Compilers for Parallel Computers, Malaga, Spain, June 1995.

"Detection and Recovery of Endangered Variables Caused by Instruction Scheduling," ACM SIGPLAN Symposium on Programming Language Design and Implementation, Albuquerque, NM, June 1993.

"Evicted Variables and the Interaction of Global Register Allocation and Symbolic Debugging," ACM SIGPLAN Symposium on Principles of Programming Languages, Charleston, SC, January 1993.

"Modeling Instruction-Level Parallelism for Software Pipelining," IFIP WG10.3 Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Orlando, FL, January 1993.

"The Effects of Register Allocation and Instruction Scheduling on Symbolic Debugging,"Supercomputer Debugging Workshop 1992, Dallas, TX, October 1992.

Invited Industry Talks

"Debugging Optimized Code," Silicon Graphics, Inc. Compiler Group. Mountain View, CA, November 1994.

"Detection and Recovery of Endangered Variables Caused by Instruction Scheduling," Motorola, Inc. Compiler Group, Austin, TX, June 1994.

"Debugging Optimized Code," Intel Corporation Compiler Conference, Beaverton, OR, May 1992.


PROFESSIONAL ACTIVITIES

Invited Panelist

"The Influence of Internet Applications on Microarchitectures", IEEE International Conference on Computer Design (ICCD'96), Austin, TX, October 1996.

Referee

International Conferences on Architectural Support for Programming Languages and Operating Systems (ASPLOS-V & ASPLOS-VI).

International Symposiums on Computer Architecture (ISCA'20, ISCA'22 & ISCA'23).

IEEE Computer.


REFERENCES

Available upon request.