Read

• Nonphotolithographic Nanoscale Memory Density Prospects, A. DeHon, S. Goldstein, P. Kuekes, and, P. Lincoln. IEEE Trans. ON Nanotechnology, March 2005; 4(2):215-228

In your writeup please address the following:

• What basic technology constraints influence the range of architectures considered in this paper. How realistic are they?
• Which of the technology constraints is most onerous? why?
• If you could build a deterministic multiplexor which was guaranteed to be defect free, how would this bit density of molecular scale memories?
• Using the Web determine the predicted bit density of CMOS only solutions for the 65nm ITRS node. Assuming a 65nm pitch for CMOS and a 10nm pitch for the nanoscale wires, what defect rates have to be achieved in order for the molecular scale memories to have a better density?

Please email me your writeup before Thur Midnight.