Read
- Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems,
Z. Zhong, D. Wang, Y. Cui, M. Bockrath, and C. Lieber,
Science 21 November 2003; 302: 1377-1379
- Demultiplexer For a Molecur Wire Crossbar Network (MWCN DEMUX),
P. Kuekes, R. Williams, July 2001, US Patent No. 6,256,767 B1
In your writeup please address the following:
- Describe the how the manufacturing difficulty changes for the
different approaches to creating multilexures in Fig 6 and 7 of the
patent.
- Consider a 65nm CMOS process and a 10nm pitch for the nanowires.
How many molecular lines need to be addressed so that at most 50\% of
the area is overhead? (In this case overhead includes all the area not
used by the molecular wires being addressed.) How is this different
for multiplexors in Figs 6 and 7.
- How much time does it take, when using the multiplexor in fig 7,
to figure out which wires are selected for a given address.
- How much memory is needed to store the lookup table which maps
addresses to particular nanowires?
- What Is the area overhead for a multiplexor constructed using the
decoder described in Zhong, et. al.?
- Explain how the pattern needed to create a multiplexor could be
created for the Zhong multiplexor.
Please email me your writeup before Wed Midnight.