Discussions
Friday 9/26/03
Wednesday 10/1/03
Friday 10/3/03
Wednesday 10/8/03
Friday 10/10/03
Reconfigurable Computing:
- Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu,
Srihari Cadambi, R. Reed Taylor, Ronald Laufer. PipeRench: A
Coprocessor for Streaming Multimedia Acceleration,
in Proceedings of the
26th Annual International Symposium
on Computer Architecture, May 1999.
- R. Razdan and M.D. Smith.
A High-Performance Microarchitecture with Hardware-Programmable Functional Units
, in Proceedings of the
27th International
Symposium on Microarchitecture (Micro-27), pages 172-180, November 1994.
- João M. P. Cardoso and Mário P. Véstias.
Architectures and Compilers to Support Reconfigurable Computing,
ACM Crossroads,
August 1999.
- Multimedia Support:
- Brucek Khailany, Willaim Dally, et. al., Imagine: Media Processing with Streams in IEEE Micro, Mar/April 2001.
- Parthasarathy Ranganathan, Sarita Adve, and Norman P. Jouppi,
Performance of Image and Video Processing with General-Purpose Processors
and Media ISA Extensions, in Proceedings of the
26th International
Symposium on Computer Architecture, May 1999.
- Linley Gwennap. Digital, MIPS Add Multimedia Extensions,
Microprocessor Report, 10(15), November 18, 1996.
- Keith Diefendorff. Pentium III = Pentium II + SSE,
Microprocessor Report, 13(3), March 8, 1999.
- Pipelining:
- A. Hartstein, Thomas R. Puzak,
The Optimum Pipeline Depth for a Microprocessor,
in ISCA, May 2002.
- M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays,
in ISCA, May 2002.
- Eric Sprangle, Doug Carmean,
"
Increasing Processor Performance by Implementing Deeper Pipelines",
in ISCA, May 2002.
- V. Agarwal, M.S. Hrishikesh, S.W. Keckler, and D.C. Burger
Clock Rate versus IPC: the End of the Road for Conventional Microarchitectures,
in ISCA, June, 2000. .
- Glenn Reinman, Todd Austin, Brad Calder,
"
A Scalable Front-End Architecture for Fast Instruction Delivery",
in ISCA, 1999.
- S. Palacharla, N. P. Jouppi, J. E. Smith,
"
Complexity-Effective Superscalar Processors",
in ISCA, 1997.
- Critical Path
- Brian Fields, Rastislav Bodik, Mark D. Hill
Slack: Maximizing Performance under Technological Constraints,
in ISCA, May 2002.
- Brian Fields, Shai Rubin, Rastislav Bodik
Focusing Processor Policies via Critical-Path Prediction,
in ISCA, July 2001.
- Ryan Rakvic, Bryan Black, Deepak Limaye, John P. Shen
Non-vital Loads,
in HPCA, 2002.
- Srikanth T. Srinivasan, Roy Dz-ching Ju, Alvin R. Lebeck, Chris Wilkerson
Locality vs. Criticality,
in ISCA, July 2001.
- Predication and IA-64:
- David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias,
Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, and
Wen-mei W. Hwu. Integrated Predicated and Speculative Execution in
the IMPACT EPIC Archtecture, in Proceedings of the
25th
International Symposium on Computer Architecture, July 1998.
- Peter Christy. IA-64 and Merced--What and Why,
Microprocessor Report, 10(17), December 30, 1996.
- Peter Song. Demystifying EPIC and IA-64,
Microprocessor Report, January 28, 1998.
- Linley Gwennap. Intel Discloses New IA-64 Features,
Microprocessor Report, 13(3), March 8, 1999.
- Linley Gwennap. IA-64: A Parallel Instruction Set,
Microprocessor Report, 13(7), May 31, 1999.
- Prefetching Pointer-Based Applications:
- Z. Wang, D. Burger, K. S. McKinley, S. R. Reinhardt, C. C. Weems,
"
Guided Region Prefetching: A Cooperative Hardware/Software Approach",
in ISCA, 2003.
- Suleyman Sair, Timothy Sherwood, Brad Calder,
"
Quantifying Load Stream Behavior",
in HPCA, 2002.
- Trishul M. Chilimbi, Martin Hirzel,
"
Dynamic Hot Data Stream Prefetching for General-Purpose Programs",
in PLDI, 2002.
- Chi-Keung Luk and Todd C. Mowry.
Compiler-Based Prefetching for
Recursive Data Structures, in Proceedings of the Seventh
International Conference on Architectural Support for Programming Languages
and Operating Systems, pages 222-233, October 1996.
- Amir Roth and Gurindar S. Sohi.
Effective Jump Pointer Prefetching for Linked Data Structures,
in Proceedings of the
26th Annual International Symposium
on Computer Architecture, May 1999.
- Branch Prediction:
- Cliff Young, Nicolas Gloy, and Michael D. Smith. A Comparative
Analysis of Schemes for Correlated Branch Prediction, in
Proceedings of the 22nd Annual International Symposium on Computer
Architecture, May 1995.
- Timothy Heil, Zak Smith, and James E Smith. Improving Branch
Predictors by Correlating on Data Values, in Proceedings of the
32nd Annual International Symposium on Microarchitecture, November 1999.
- Joel Emer and Nikolas Gloy. A Language for Describing
Predictors and its Application to Automatic Synthesis, in
Proceedings of the
24th Annual International Symposium on Computer
Architecture, June 1997.
- Trace Caches:
- Eric Rotenberg, Steve Bennett, and James E. Smith. A Trace Cache
icroarchitecture and Evaluation, in IEEE Transactions on Computers,
48(2):111-120, February 1999.
- Bryan Black, Bohuslav Rychlik, and John Paul Shen. The
Block-based Trace Cache, in Proceedings of the 26th Annual
International Symposium on Computer Architecture, pages 196-207, May 1999.
- Value Prediction:
- Vector Processors:
- Roger Espasa, Mateo Valero, James E. Smith,
"
Vector Architectures: Past, Present and Future",
in Supercomputing, 1998.
- C. Kozyrakis, D. Patterson,
"
Vector vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks",
in MICRO, 2002.
- C. Kozyrakis, D. Patterson,
"
Overcoming the Limitations of Conventional Vector Processors",
in ISCA, 2003.
- Power:
- Michael Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar,
"
Gated-Vdd: A Vircuit Technique to Reduce Leakage in Deep-Submicron Cache Memories",
in ISLPED, 2000.
- R. Sasanka, C. J. Hughes, S. V. Adve
"
Joint Local and Global Hardware Adaptations for Engergy",
in ASPLOS, October 2002.
- K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranaranyanan, D. Tarjan,
"
Temperature-Aware Microarchitecture",
in ISCA, June 2003.
- A. Anantaraman, K. Seth, K. Patil, E. Rotenberg, F. Mueller,
"
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems",
in ISCA, June 2003.
- Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, and Kaushik Roy,
Reducing
Set-Associative Cache Energy via Selective Direct-Mapping and
Way-Prediction, in MICRO, December 2001.
- Emmett Witchel, Sam Larsen, C. Scott Ananian, Krste Asanovic,
Direct
Addressed Caches for Reduced Power Consumption in MICRO, December, 2001.
- Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor Mudge,
Drowsy
Caches: Techniques for Reducing Leakage Power in ISCA, 2002.
- Multiprocessors on a chip:
- K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, C. R. Moore,
"
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture,"
in ISCA, 2003.
- R. Nagarajan, K. Sankaralingam, D.C. Burger, and S.W. Keckler. "A
Design Space Evaluation of Grid Processor Architectures,"
in 34th International Symposium on Microarchitecture (MICRO),
pp. 40-51, December, 2001.
- Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff,
Fae Ghodrat, Ben Greenwald, Henry Hoffman, Jae-Wook Lee, Paul Johnson,
Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman,
Volker Strumpen Matt Frank, Saman Amarasinghe and Anant Agarwal,
The
Raw Microprocessor: A Computational Fabric for Software Circuits and
General Purpose Programs, IEEE Micro, Mar/Apr 2002.
- Ho-Seop Kim, James E. Smith,
"
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing,"
in ISCA, 2002.
- Paramjit S. Oberoi and Gurindar S. Sohi, Out-of-Order Instruction Fetch using Multiple
Sequencers, The 2002 International Conference on Parallel
Processing (ICPP-31), Aug. 18-21, 2002.
- Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar,
"
Multiscalar Processors,"
in ISCA, 1995.
- Memory Consistency Models:
- S. V. Adve, V. S. Pai, and P. Ranganathan.
Recent Advances in
emory Consistency Models for Hardware Shared-Memory Systems, in Proceedings of the IEEE, special issue on distributed shared-memory, March
1999, 445-455.
- Chris Gniady, Babak Falsafi, and T. N. Vijaykumar.
Is SC +
ILP = RC?,
in Proceedings of the 26th Annual International Symposium
on Computer Architecture, pages 162-171, May 1999.
- Mark D. Hill. Multiprocessors Should Support Simple Memory
Consistency Models,, in IEEE Computer, August 1998.
- Fault Tolerance and Recovery:
- Daniel J. Sorin, Milo K. Martin, Mark D. Hill, David A. Wood,
"
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery",
in ISCA, 2002.
- S. S. Mukherjee, M. Kontz, S. K. Reinhardt,
"
Detailed Design and Evaluation of Redundant Multithreading Alternatives",
in ISCA, 2002.
- Prediction in Memory Systems:
- Timothy Sherwood, Suleyman Sair, Brad Calder,
"
Phase Tracking and Prediction",
in ISCA, 2003.
- Kevin M. Lepak, Mikko H. Lipasti,
"
Temporally Silent Stores",
in ASPLOS, 2002.
- An-Chow Lai, Cem Fide, Babak Falsafi,
"
Dead-Block Prediction and Dead-Block Correlating Prefetchers",
in ISCA, 2001.
- Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi,
"
Dynamic Speculation and Synchronization of Data Dependences",
in ISCA, 1997.
- Brannon Batson, T. N. Vijaykumar,
"
Reactive-Associative Caches",
in PACT, 2001.
- Simultaneous Multithreading:
- Susan Eggers, Joel Emer, Henry Levy, Jack Lo, Rebecca Stamm, and Dean
Tullsen. Simultaneous Multithreading: A Platform for
Next-generation Processors, in IEEE Micro, September/October 1997,
pages 12-18.
- Jack Lo, Susan Eggers, Joel Emer, Henry Levy, Rebecca Stamm, and Dean
Tullsen. Converting Thread-Level Parallelism Into Instruction-Level
Parallelism via Simultaneous Multithreading, in ACM Transactions on
Computer Systems, August 1997, pages 322-354.
- Speculative Multiprocessing:
- Lance Hammond, Mark Willey, and Kunle Olukotun.
Data
Speculation Support for a Chip Multiprocessor, in Proceedings of
the Eighth ACM Conference on Architectural Support for Programming
Languages and Operating Systems, San Jose, California, October 1998.
- J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai and Todd C. Mowry.
A Scalable Approach to Thread-Level Speculation, in
Proceedings of the 27th Annual International Symposium
on Computer Architecture, pages 1-12, June 2000.
- Parallel Applications:
- Ravi Rajwar, James R. Goodman,
"
Transactional Lock-Free Execution of Lock-Based Programs",
in ASPLOS, 2002.
- Dongming Jiang and Jaswinder Pal Sing.
Scaling Application Performance
on a Cache-coherent Multiprocessor,
in Proceedings of the 26th Annual International Symposium
on Computer Architecture, pages 305-316, May 1999.
- Hongzhang Shan and Jaswinder Pal Singh.
A Comparison of the
PI, SHMEM and Cache-coherent Shared Address Space Programming Models on
the SGI Origin2000, in Proceedings of the International Conference
on Supercomputing, June 1999.
- Chris Holt, Jaswinder Pal Singh and John Hennessy.
Application and Architectural Bottlenecks in Distributed Shared Memory
ultiprocessors, in Proceedings of the 22nd International Symposium
on Computer Architecture, pages 134-145, May 1996.
- Multithreading:
- Von Eiken, Et. Al. Active Messages...
in Proceedings of the 26th Annual International Symposium
on Computer Architecture, May 1992.
- Spertus, Et. Al. Comparison of J-Machine and CM-5 in Proceedings of the International Conference
on Supercomputing, June 1994.
- Culler, Et. Al.Threaded Abstract Machine... in APLOS