Pegasus Opcodes

The basic catagories

Opcodes for the operations fall into several basic catagories.

logical and arithmetic	These include all the operations you would normally thing would be in an IR. integer +,-,,etc. Floating point +,-,,etc. Logical operations, comparisons, etc.
	fp_add fp_div fp_mul fp_neg fp_sub add div mul muluh neg rem sub and asr cmpl land lor lsl lsr or xor eq le leq ne not
Memory	These include load and store operations as well as operations which control the tokens that determine the order that memory operations can be invoked.
	ldcont lod str tkand tkgen
register type	These include operations which transfer data from the input to the output, potentially with some form of control. They generally are not in traditional IRs, but are here to help with optimizations such as pipelining.
	hold none nop reg uninit
Intra-hyperblock flow	These operations guide data flow within the hyperblock. It includes mux operations and hold operations
	mux
Inter-hyperblock flow	These operators guide data from one hyperblock to another (or potentially to the head of the current one if the current hyperblock is a loop.) Included here are mu, eta, and switch nodes.
	eta mu switch
Inter-Function flow	There include operations for calling a function, returning from a function, and related tasks, e.g., arguments, stack frames, etc.
	arg cal cont ret
Misc	There include miscellaneous operations
	cast const
Epoch Related	The operations in this catagory are used to create and manage memory epochs and the memory operations that used epochs.
	ecal econt eret elod estr ecreate epoch ehc elc eld end
Other	Ignore these for now.
	chk lod_nopred lod_pred lvmerge str_nopred str_pred tokrelease lsq memap memdemux memmux memport memrvouz tlod tstr frame pop sp create delete network

The operations

Opcode	Inputs	Outputs	Dotty text	Dotty Graphic
	Description
add	2	1	+
	(Integer arithmetic)
and	2	1	&
	(bitwise and logical ops)
arg	0	1
	(Inter-Function flow) This represents an incoming argument to the function. There is no input wire
asr	2	1	>>
	(bitwise and logical ops)
cal	-1	-1	call
	(Inter-Function flow) In addition to the address (first arg) and the arguments to the callee (next n args for an n-arg call) there are four extra inputs SP, pred, token, crt. (Old Simulator) 2 out: val,token; (New simulator) 4 out: val,SP,crt,token .
cast	1	1	(t)
	(misc) This cases the input to the type of the ouput. May not be C casts, e.g., can cast a 16 bit signed into a 3 bit unsigned.
chk	3	1	chk
	(misc) two address to check for equivalence, 3rd argument unique id
cmpl	1	1	~
	( bitwise and logical ops)
const	0	1
	(misc) The constant is represented as an immed in the node. It has no inputs.
cont	-1	-1	cont
	(Inter-Function Flow) call continuation: in: data, token. out: data, token (Old Simulator). call continuation: in: data, SP, crt, token out: data, SP, crt, token (New Simulator)
create	1	2	C
	( misc) 1 in: crt, 2 out: address, token: allocate a symbol
delete	2	1	D
	( misc) in: address, token; out: token: destroy a symbol
div	3	1	/
	(Integer arithmetic) 3-rd input is a predicate. If false, don't perform the addition.
ecal	-1	4	Ecall
	( Epoch based call infrastructure (works with the new simulator and lowered IR only)) 4 out: val,SP,crt,epochId lowered: four extra in: SP, pred, epochId, crt
econt	4	4	Econt
	( Epoch based call infrastructure (works with the new simulator and lowered IR only)) call continuation: in: data, SP, crt, epochId out: data, SP, crt, epochId
ecreate	-1	3	EC
	( Epoch related) epoch ids of epochs that have to complete before our epoch ops can execute second to last input: enabling token, cannot execute before getting this (?may not be needed?) last input: tree connection input outputs: 0 epoch-id, 1 completion token (?may not be needed?), 2 tree output
ehc	-1	2	EHC
	( special epoch nodes for loops without calls) epoch ids of epochs that have to complete before out epoch ops can execute second to last input: enabling token, cannot execute before getting this (?may not be needed?) last input: tree connection input outputs: 0 epoch-id, 1 tree output
elc	2	2	ELC
	( special epoch nodes for loops without calls) inputs: 0 epoch-id of prior chained epoch, 1 tree connection input outputs: 0 epoch-id, 1 tree connection output
eld	3	2	ELD
	(special epoch nodes for loops without calls) inputs: 0 epoch-id of prior chained epoch, 1 predicate, 2 tree connection input outputs: 0 completion token (?may not be needed?), 1 tree output
elod	4	2	E=[ ]
	( Epoch based memory operations) inputs: address, predicate, epochid,treein; out = data,treeout
end	0	0	###	Nada
	(misc) Never present.
epoch	1	1	E
	(Epoch related) 1 in: token 1 out: token to be sent to all epoch operations in parallel
eq	2	1	==
	(comparisons)
eret	4	0	Eret
	( Epoch based call infrastructure (works with the new simulator and lowered IR only)) inputs: returned value, PC, epochId, crt
estr	4	1	E[ ]=
	( Epoch based memory operations) inputs: address, data, predicate, epochid; out = treeout
eta	3	1	n
	(Inter-hyperblock flow) 3 in: val, pred, crt, 1 out: val. If pred is true and crt has arrived, then pass pass val to output.
fp_add	2	1	+
	( FP stuff)
fp_div	3	1	/
	( FP stuff) 3-rd input is predicate
fp_mul	2	1	*
	( FP stuff)
fp_neg	1	1	-
	( FP stuff)
fp_sub	2	1	-
	( FP stuff)
frame	1	2	frm
	( OBS: This applies to the old simulator only ) create a frame on the stack; in=token, out=sp, token
hold	2	1	H
	( ) loop invariant op; in: data, predicate; out: data. If predicate is true, pass data to output.
land	-1	1	&&
	( bitwise and logical ops) logical and. Can take many inputs, all evaluated and anded together.
ldcont	1	1	=[+]
	( memory ops) inputs: data; out = data
le	2	1	<
	( comparisons)
leq	2	1	<=
	( comparisons)
lod	3	2	=[ ]
	( memory ops) inputs: address, predicate, token; out = data, token. if predicate is true, issue load when token arrives. Return data and when load performed, issue token.
lod_nopred	5	1	N=[ ]
	( Hardware Ops for Memory) inputs: address, token, global token path, local token path, value path; outputs: tree access
lod_pred	5	2	P=[ ]
	( Hardware Ops for Memory) inputs: address, token, global token path, local token path, value path; outputs: tree access, false token
lor	-1	1	\|\|
	( bitwise and logical ops) logical or of multiple inputs.
lsl	2	1	<<
	( bitwise and logical ops)
lsq	2	2	LSQ
	( Memory Tree) tree reply
lsr	2	1	>>
	( bitwise and logical ops)
lvmerge	2	1	LVU
	( Hardware Ops for Memory) inputs: val, token; outputs: val
memap	1	1	MAP
	( Memory Tree) node representing the memory access port
memdemux	1	-1	MD
	( Memory Tree) node to build tree from the memory access point to the circuits
memmux	2	1	MM
	( Memory Tree) node to build tree from circuits to the memory access point
memport	1	1	MPORT
	( Memory Tree) inputs: memory access; outputs: memory reply
memrvouz	-1	-1	MRV
	( Memory Tree) girish's memory tree node
mu	-1	2	u
	( control-flow) loop entry point; 2nd out is hyper #, used by crt. This has n inputs, 1 of which will be valid. When it arrives, pass it onto the output. indicate which one arrived in the second output.
mul	2	1	*
	( Integer arithmetic)
muluh	2	1	muluh
	( Integer arithmetic) 32x32->32 high bits of multiply
mux	-1	1	?:
	(Intra-hyperblock flow) 2n inputs. first n inputs are data, second n inputs are predicates. Only 1 predicate should eval to true, its data input is sent to the output.
ne	2	1	!=
	( comparisons)
neg	1	1	-
	( Integer arithmetic)
network	-1	-1	NET
	( network node) used in simulator to model the network
none	0	1	???	Nada
	(misc ) different from no-operation: temporary placeholder
nop	1	1
	(register type) copy input to output: 0 clock cycles
not	1	1	!
	( comparisons)
or	2	1	\|
	( bitwise and logical ops)
pop	1	1	pop
	( OBS: This applies to the old simulator only ) pop a frame of the stack; in=token, out=token
reg	1	1
	(register type ) copy input to output: 1 clock cycle
rem	3	1	%
	( Integer arithmetic) 3-rd in is predicate
ret	4	0	ret
	(Inter-Function flow) inputs: returned value, PC, token, crt. return value to caller at PC when you get token and crt.
sp	1	1	sp
	( OBS: This applies to the old simulator only ) get current SP value; in=token, out=SP
str	4	1	[ ]=
	( memory ops) inputs: address, data, predicate, token; out = token. if predicate is true, perform store of data into address. When store is performed, issue token.
str_nopred	5	1	N[ ]=
	( Hardware Ops for Memory) inputs: address, data, token, global token path, local token path; outputs: tree access
str_pred	5	2	P[ ]=
	( Hardware Ops for Memory) inputs: address, data, token, global token path, local token path; outputs: tree access, false token
sub	2	1	-
	( Integer arithmetic)
switch	-1	1	Y
	(Inter-hyperblock flow) n inputs; last one is hyper number; 1 out: val The last input determines which one of the first n inputs is passed to the output.
tkand	-1	1	V
	( tokens) token and. And all the inputs to produce a token on the output.
tkgen	2	1	G
	( tokens) token generator: 2 in: token, predicate; 1 out token
tlod	4	3	T=[ ]
	( Memory Tree load store ops) inputs: address, predicate, token, treein; outputs: data, token, treeout
tokrelease	1	2	TKR
	( Hardware Ops for Memory) inputs: tree access; outputs: tree access, token
tstr	5	2	T[ ]=
	( Memory Tree load store ops) inputs: address, data, predicate, token, treein; outputs: token, treeout
uninit	0	1	???	Nada
	(misc ) uninitialized value
xor	2	1	^
	( bitwise and logical ops)