Paper Review  for Seminar 3

Title: XC4000E and XC4000X Series Field Programmable Gate Arrays, Product Specification

Author: Xilinx Corp.

Answer the following questions:
  1. Using the values in Table 1, determine the number of "gates" are contained in a CLB. If a D flip-flop is approximately 10 gates, how much logic is contained in a single 4-input LUT (ignore the 3-input LUTs in the CLB).
  2. Notice that all the cells in the FPGA have the same functionality. Give at least two advantages and two disadvantages to having a homogeneous fabric such as this.
  3. How will gate-level netlists that were originally designed for custom silicon map to the XC4000E? How would circuits designed specifically for FPGAs compare to circuits designed for custom silicon?
  4. Using Figure 14, describe how the fast carry logic can be used to generate a carry function for a full adder. Reminder: The function for Cout for a full adder is:

    Cout = (A & B) | (A & Cin) | (B & Cin)

    Where Cin is the carry in, and A and B are the two inputs. Ampersand is the logical AND, and the bar (|) is the logical OR. What gates or MUXs are used, and what paths are enabled?

Review by: YOUR NAME GOES HERE