iWarp Project
The iWarp system and project are described in
iWarp: Anatomy of a Parallel Computing System,
by Thomas Gross and David R. O'Hallaron,
published by MIT Press (Mar 1998).
This book describes the LIW processor, the inter-processor
communication system, the software, and a number of applications that
used iWarp systems.
Foreword by
Gordon Bell (Microsoft Research), afterword by
H. T. Kung (Harvard).
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[01-Mar-98]
Table of Contents
The iWarp project was started in 1988 to investigate issues involved
in building and using high performance computer systems with powerful
communication support. The project lead to the construction of the
iWarp machines, jointly developed by Carnegie Mellon University and
Intel Corporation.
The basic building block of the iWarp system is a full custom
VSLI component integrating a LIW microprocessor, a network interface
and a switching node into one single chip of 1.2cm x 1.2cm silicon.
Technical data of iWarp systems
Computation agent of single cell:
- Processor type: 32bit RISC with 96bit LIW
- Clock speed: 20MHz
- Integer performance: 20 Mips
- Floating point support: 32bit IEEE and 64bit IEEE
- Foating point performance: 20 MFlops and 10MFlops
- Network access through gates in register file up to 4 x 40 MB/s
Communication agent of single cell:
- Switching performance in node: 160 MB/s to 320 MB/s
- Links: 4 x 40MB/s, full duplex
- Logical/virtual channels: 20, configurable freely in all 4 directions and 2 pools.
- Clock speed: 40MHz
Memory System of single cell:
- Memory configurations:
- 512kBytes to 4MBytes static RAM or/and 16MBytes dynamic RAM.
- Memory access latency 100ns static, 200ns dynamic
- Memory access bandwidth 160 MB/s
- Direct memory access agents for communication (spools): 8
Parallel system configurations:
- 4 cells up to 1024 cells in n x m torus configurations.
- Typical system: 64 cells, 8x8 torus, 1.2 GFlop/s peak.
- Sustained performance (64 cells):
- Dense matrix multiply: 1150 MFlop/s
- Sparse matrix multiply: 400 MFlop/s
- FFT: 700 MFlop/s
iWarp status
Intel Corporation has announced the iWarp systems as product in 1989
and built iWarp systems with over 1500 nodes since then. The first
iWarp prototype system was delivered to Carnegie Mellon in Summer 1990
and in Fall CMU received the first 64 cell systems. All three full
speed production systems were delivered in 1991.
With the creation of the Intel Supercomputing Systems Division in
Summer 1992 the iWarp know how was merged with the iPSC product line.
Intel kept iWarp as a product but stopped actively marketing it.
As of today, the start of 1995 all three iWarp systems at CMU are in
still in daily use. Surprisingly there are a few applications (e.g.
in real time vision) for which iWarp is still the best machine, 3
years after it has been delivered. The high speed static memory and
the high performance low latency communication system make iWarp a
very well suited target for research efforts and many "proof of
concept" applications.
Pictures of an iWarp system
Click small pictures for full size JPEG.
left: The iWarp chip (VLSI component)
right: The iWarp quad cell board (4 processors +
memory + communication)
left: 64 iWarp cells mounted in a 19" rack (power: 1.2 GFlop/s).
right: iWarp system cabinet with up to 256 cells.
General info
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