Guei-Yuan (Ken) Lueh

PERSONAL DATA

    Home Address:   1239 Quail Creek Circle
                    San Jose, CA 95120 USA
    Office Address: Intel Corporation SC12-303
                    2200 Mission College Blvd.
                    Santa Clara, CA 95052-8119 USA 

    Email:          Guei-Yuan.Lueh@intel.com 
    Web Page:       http://www.cs.cmu.edu/~gyl 
    Phone Number:   Office: (408) 653-9655    
                    Fax:    (408) 653-8511
                    Home:   (408) 323-9534

OBJECTIVE

An industrial research and development position working on system software and applications. Experienced in most aspects of compiler implementation including optimization, data alignment, retargetable code generation, register allocation, instruction scheduling, and object-oriented compiler frameworks.

EDUCATION

1993 - 1997, Carnegie Mellon University, Pittsburgh PA

Ph.D. in Electrical and Computer Engineering 1997

Advised by: Professor Thomas Gross, School of Computer Science

Thesis: Fusion Based Register Allocation

1992 - 1993, Carnegie Mellon University, Pittsburgh PA

M.S. in Electrical and Computer Engineering

1981 - 1985, Tamkang University, Taipei Taiwan

B.S. in Computer Science

RESEARCH EXPERIENCE

1997 - present: Microcomputer Research Lab., Intel Corporation

Implemented JVM debugging interface support.
Developed Java dynamic optimization techniques for Intel's iA32 and iA64 (Merced) architecture.
Developed a Java Just-In-Time (JIT) compiler for Intel Pentium and Pentium Pro architecture.

1993 - 1997: School of Computer Science, Carnegie Mellon University

Developed a register allocation approach that deals with live range splitting, spilling and register assignment in an integrated fashion.
Participated in the development of cmcc, a retargetable optimizing ANSI C compiler (written in C++) with code generators for MIPS, SPARC, and iWarp.
Developed object-oriented frameworks for instruction scheduling and register allocation in the cmcc compiler.

1990 - 1993: School of Computer Science, Carnegie Mellon University (Research Programmer)

Developed a global data dependence analysis module for the Intel iWarp optimizing compiler, an optimizing C compiler for a VLIW machine. This module identifies potential memory aliases inside loops for use by the software pipeliner.
Developed a pre-scheduling module for the Intel iWarp optimizing compiler. This module eliminates unnecessary moves, thus shortening the critical path and decreasing resource requirements, before software pipelining.
Developed a data alignment module for the Fx parallelizing FORTRAN compiler. This module analyzes array reference patterns and provides array alignment information that guides the data distribution phase to generate good communication patterns among array occurrences.

1987 - 1989: Electronics Research & Service Organization, Taiwan (System Design Engineer)

Developed a machine-independent global optimizer based on Fred Chow's Ph.D. thesis.

TEACHING EXPERIENCE

Carnegie Mellon University, Pittsburgh PA

superscalar processor design

FELLOWSHIP AWARD

Intel Foundation Graduate Fellowship Award (1996)

PUBLICATIONS

M. Cierniak, G.Y. Lueh, and J.M. Stichnoth, Practicing JUDO: Java Under Dynamic Optimizations, Proc. ACM SIGPLAN Symp. on Programming Language Design and Implementation, June 2000, pages 13 - 26.
J.M. Stichnoth, G.Y. Lueh and M. Cierniak, Support for Garbage Collection at Every Instruction in a Java Compiler, Proc. ACM SIGPLAN Symp. on Programming Language Design and Implementation, May 1999, pages 118 - 127.
A. Adl-Tabatabai, M. Cierniak, G.Y. Lueh, V.M. Parikh and J.M. Stichnoth, Fast, Effective Code Generation in a Just-In-Time Java Compiler, Proc. ACM SIGPLAN Symp. on Programming Language Design and Implementation, June 1998, pages 280 - 290.
G.Y. Lueh and T. Gross, Call-cost Directed Register Allocation, Proc. ACM SIGPLAN Symp. on Programming Language Design and Implementation, June 1997, pages 296 - 307.
A. Adl-Tabatabai, T. Gross and G.Y. Lueh, Code Reuse in an Optimizing Compiler, Proc. ACM Conference on Object-Oriented Programming Systems, Languages, and Applications (OOPSLA'96), pages 51 - 68. October 1996.
G.Y. Lueh, T. Gross and A. Adl-Tabatabai, Global Register Allocation Based on Graph Fusion, Ninth Workshop on Languages and Compilers for Parallel Computers, August 1996. pages 246 - 265.
G.Y. Lueh, Issues in Register Allocation by Graph Coloring, Technical Report CMU-CS-96-171, School of Computer Science, Carnegie Mellon University, November 1996.
G.Y. Lueh, T. Gross and A. Adl-Tabatabai, Global Register Allocation Based on Graph Fusion, Technical Report CMU-CS-96-106, School of Computer Science, Carnegie Mellon University, March 1996.
A. Adl-Tabatabai, T. Gross, G.Y. Lueh and J. Reinders. Modeling Instruction-Level Parallelism for Software Pipelining, Proc. of the IFIP WG10.3 Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Orlando, FL, pages 321-330. North Holland, January 1993.
T. Gross, S. Hinrichs, G. Lueh, D. O'Hallaron, J.Stichnoth, and J. Subholk. Compiling Task and Data Parallel Programs for iWarp, Workshop on Languages, Compilers, and Run-time Environments for Distributed Memory Machines, Sep. - Oct., 1992.

REFERENCES

Available upon request