A Sorting Computational Sensor
V. Brajovic and T. Kanade
Tech. report CMU-RI-TR-96-01, Robotics Institute, Carnegie Mellon University, February, 1996.

Abstract

The need for low-latency vision systems is growing; high speed visual servoing and vision-based human computer interface. In this paper we present a new intensity-to-time processing paradigm suitable for low-latency massively parallel global computation over fine-grained data such as images. As an example if a low-latency global computation, we have developed a VLSI sorting computational sensor - a sensor which sorts all pixels of an input image by their intensities, as the image is being sensed. The first sorting sensor prototype is a 21 by 26 array f cells. It detects an image focused theron and computes the image of indices never saturates and has uniform histogram. Under user's control, the chip can perform other operations including simple segmentation and labeling.

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Text Reference

V. Brajovic and T. Kanade, A Sorting Computational Sensor, tech. report CMU-RI-TR-96-01, Robotics Institute, Carnegie Mellon University, February, 1996.

BibTeX Reference

@techreport{Brajovic_1996_396,
author = "Vladimir Brajovic and Takeo Kanade",
title = "A Sorting Computational Sensor",
institution = "Robotics Institute, Carnegie Mellon University",
month = "February",
year = "1996",
number = "CMU-RI-TR-96-01",
address = "Pittsburgh, PA"
}