Dong Wang

Publications

Sample Course Projects

• 18-545 Advanced Digital Design Project.
• 18-742 Advanced Computer Architecture.
• 18-760 VLSI CAD: Logic to Layout.
• 15-851 Computation and Deduction.

A simple translator from Verilog to SMV based on Synopsys Design Compiler and ver structural Verilog compiler.

Academic Advisor: Prof. Edmund M. Clarke

Research Interests:

• Gigascale Silicon Research Center
• Model Checking