|
In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '00)
Peter M. Kamarchik, Steven Sinha, and Seth Copen Goldstein
Napa, CA
Apr 1990
@inproceedings{KSS00,
author = {Kamarchik, Peter M. and Sinha, Steven and Goldstein, Seth
Copen},
title = {Fault Tolerance in Run-time Reconfigurable Architectures},
booktitle = {IEEE Symposium on FPGAs for Custom Computing Machines
(FCCM '00)},
year = {2000},
month = {Apr},
address = {Napa, CA},
keywords = {PipeRench, Fault and Defect Tolerance},
}
Related Papers
Fault And Defect Tolerance |
|
Nonphotolithographic Nanoscale Memory Density Prospects | pdf bib | |
Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln.
IEEE Transactions on Nanotechnology,
volume 4, pages 215–228, Mar 1990.
|
| @article{lincoln-tnano05,
title = {Nonphotolithographic Nanoscale Memory Density Prospects},
abstract = {Technologies are now emerging to construct
molecular-scale electronic wires and switches using bottom-up
self-assembly. This opens the possibility of constructing
nanoscale circuits and memories where active devices are just a
few nanometers square and wire pitches may be on the order of ten
nanometers. The features can be defined at this scale without
using photolithography. The available assembly techniques have
relatively high defect rates compared to conventional
lithographic integrated circuits and can only produce very
regular structures. Nonetheless, with proper memory organization,
it is reasonable to expect these technologies to provide memory
densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
power requirements under 0.6 W/Tb/s for random read operations.},
url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
journal = {IEEE Transactions on Nanotechnology},
author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
and Lincoln, Patrick},
year = {2005},
month = {Mar},
volume = {4},
issue = {2},
pages = {215-228},
keywords = {Fault and Defect Tolerance, electronic nanotechnology,
memory density, memory organization, molecular electronics},
doi = {10.1109/TNANO.2004.837849},
}
|
|
Computing Without Processors | bib | |
Seth Copen Goldstein.
In International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'04),
pages 29–32, Jun 1990.
|
| @inproceedings{goldstein04-ersa04,
author = {Goldstein, Seth Copen},
title = {Computing Without Processors},
booktitle = {International Conference on Engineering of
Reconfigurable Systems and Algorithms (ERSA'04)},
abstract = {The continuation of the remarkable exponential increases
in processing power over the recent past faces imminent
challenges due in part rising cost of design and manufacturing
and the physics of deep-submicron semiconductor devices. In this
talk we will discuss a promising alternative to ever more complex
processors, application specific hardware (ASH). The ASH model is
based on compiling high-level programs directly into circuits,
which can either be fabricated as ASICs or more reasonably
converted in configurations for reconfigurable devices. We will
discuss the challenges involved in compiling sequential
programming languages into circuits and the challenges in
implementing those circuits in a scalable and power efficient
manner.},
address = {Las Vegas, NV},
month = {Jun},
year = {2004},
pages = {29--32},
keywords = {Reconfigurable Computing, Electronic Nanotechnology,
Fault and Defect Tolerance},
}
|
|
Defect Tolerance at the End of the Roadmap | bib | |
Mahim Mishra and Seth Copen Goldstein.
In Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation,
1990.
|
| @incollection{mishra-nqmc04,
title = {Defect Tolerance at the End of the Roadmap},
booktitle = {Nano, Quantum and Molecular Computing: Implications to
High Level Design and Validation},
author = {Mishra, Mahim and Goldstein, Seth Copen},
year = {2004},
editor = {Sandeep K. Shukla and R. Iris Bahar},
publisher = {Kluwer Academic Publishers},
isbn = {1-4020-80670},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing,Phoenix,molecular
electronics},
}
|
|
Translating ANSI C to Asynchronous Circuits | pdf bib | |
Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein.
In 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '04),
Apr 1990.
|
| @inproceedings{budiu-async04,
title = {Translating ANSI C to Asynchronous Circuits},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
booktitle = {10th IEEE International Symposium on Asynchronous
Circuits and Systems (ASYNC '04)},
author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
Tiberiu and Goldstein, Seth Copen},
address = {Crete, Greece},
year = {2004},
month = {Apr},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
Computing},
}
|
|
Defect Tolerance After the Roadmap | pdf bib | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the 10th International Test Synthesis Workshop (ITSW),
Mar 1990.
|
| @inproceedings{mishra-itsw03,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Defect Tolerance After the Roadmap},
booktitle = {Proceedings of the 10th International Test Synthesis
Workshop (ITSW)},
month = {Mar},
year = {2003},
address = {Santa Barbara, {CA}},
keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
Fault and Defect Tolerance},
url = {http://www.cs.cmu.edu/~seth/papers/mishra-itsw03.pdf},
}
|
|
Defect Tolerance at the End of the Roadmap | pdf bib | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the International Test Conference (ITC), 2003,
Sep 1990.
|
| @inproceedings{mishra-itc03,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Defect Tolerance at the End of the Roadmap},
booktitle = {Proceedings of the International Test Conference
({ITC}), 2003},
month = {Sep},
year = {2003},
address = {Charlotte, {NC}},
url = {http://www.cs.cmu.edu/~seth/papers/mishra-itc03.pdf},
abstract = {Defect tolerance will become more important as feature
sizes shrink closer to single digit nanometer dimensions. This is
true whether the chips are manufactured using top-down methods
(e.g., photolithography) or bottom-up methods (e.g., chemically
assembled electronic nanotechnology, or CAEN). In this paper, we
propose a defect tolerance methodology centered around
reconfigurable devices, a scalable testing method, and dynamic
place-and-route. Our methodology is particularly well suited for
CAEN.},
keywords = {Spatial Computing, Reconfigurable
Computing,Phoenix,Fault and Defect Tolerance},
}
|
|
Molecules, Gates, Circuits, Computer | pdf bib | |
Seth Copen Goldstein and Mihai Budiu.
In Molecular Nanoelectronics,
Jan 1990.
|
| @incollection{goldstein-mn03,
title = {Molecules, Gates, Circuits, Computer},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
booktitle = {Molecular Nanoelectronics},
author = {Goldstein, Seth Copen and Budiu, Mihai},
year = {2003},
editor = {Mark A. Reed and Takhee Lee},
publisher = {American Scientific Publishers},
address = {Stevenson Ranch, CA},
month = {Jan},
isbn = {1-588883-006-3},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Reconfigurable Computing,Spatial
Computing,electronic nanotechnology,molecular electronics},
}
|
|
Nano, Quantum, and Molecular Computing: Are We Ready for the Validation and Test Challenges | pdf bib talk | |
Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forest Brewer, Kaustav Banerjee, and Sankar Basu.
In Eighth IEEE International High-Level Design Validation and Test Workshop,
pages 307, Nov 1990.
|
| @inproceedings{shukla-hldvt03,
title = {Nano, Quantum, and Molecular Computing: Are We Ready for
the Validation and Test Challenges},
url = {http://www.cs.cmu.edu/~seth/papers/shukla-hldvt03.pdf},
talk = {http://www.cs.cmu.edu/~seth/hldvt03-goldstein.pdf},
booktitle = {Eighth IEEE International High-Level Design Validation
and Test Workshop},
author = {Shukla, Sandeep K. and Karri, Ramesh and Goldstein, Seth
Copen and Brewer, Forest and Banerjee, Kaustav and Basu, Sankar},
year = {2003},
month = {Nov},
pages = {307},
address = {San Francisco, CA},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,molecular electronics},
}
|
|
Reconfigurable Nanoelectronics and Defect Tolerance | bib | |
Seth Copen Goldstein.
In Proceedings of High-level design, verification, and test,
1990.
|
| @inproceedings{goldstein-hldvt03,
title = {Reconfigurable Nanoelectronics and Defect Tolerance},
author = {Goldstein, Seth Copen},
booktitle = {Proceedings of High-level design, verification, and
test},
year = {2003},
keywords = {Reconfigurable Computing, Electronic Nanotechnology,
Fault and Defect Tolerance},
}
|
|
Scalable Defect Tolerance for Molecular Electronics | pdf bib | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the 1st Workshop on Non-Silicon Computing (NSC-1),
1990.
|
| @inproceedings{mishra_goldstein_nsc1,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Scalable Defect Tolerance for Molecular Electronics},
booktitle = {Proceedings of the 1st Workshop on Non-Silicon
Computing (NSC-1)},
address = {{Cambridge, MA}},
year = {2002},
url = {http://www.cs.cmu.edu/~seth/papers/mishra_goldstein_nsc1.pdf},
abstract = {Chemically assembled electronic nanotechnology (CAEN) is
a promising alternative to CMOS-based computing. However,
CAEN-based circuits are expected to have huge defect densities.
To solve this problem CAEN can be used to build reconfigurable
fabrics which, assuming the defects can be found, are inherently
defect tolerant. In this paper, we propose a scalable testing
methodology for finding defects in reconfigurable devices.},
keywords = {Reconfigurable Computing, Phoenix,Fault and Defect
Tolerance},
}
|
|
Electronic Nanotechnology and Reconfigurable Computing | pdf bib | |
Seth Copen Goldstein.
In Proceedings of the IEEE Computer Society Workshop VLSI 2001,
pages 10, Apr 1990.
|
| @inproceedings{goldstein-wvlsi01,
title = {Electronic Nanotechnology and Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-wvlsi01.pdf},
booktitle = {Proceedings of the IEEE Computer Society Workshop VLSI
2001},
author = {Goldstein, Seth Copen},
year = {2001},
pages = {10},
month = {Apr},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing},
}
|
|
Fault Tolerance in Run-time Reconfigurable Architectures | bib | |
Peter M. Kamarchik, Steven Sinha, and Seth Copen Goldstein.
In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '00),
Apr 1990.
|
| @inproceedings{KSS00,
author = {Kamarchik, Peter M. and Sinha, Steven and Goldstein, Seth
Copen},
title = {Fault Tolerance in Run-time Reconfigurable Architectures},
booktitle = {IEEE Symposium on FPGAs for Custom Computing Machines
(FCCM '00)},
year = {2000},
month = {Apr},
address = {Napa, CA},
keywords = {PipeRench, Fault and Defect Tolerance},
}
|
|
NanoFabrics: Extending Moore's Law Beyond the CMOS Era | pdf bib | |
Seth Copen Goldstein.
In The 10th International Conference on Architectural Support for Programming Languages and Operating Systems. (ASPLOS 'IX),
Nov 1990.
|
| @inproceedings{goldstein-asplos00,
title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
booktitle = {The 10th International Conference on Architectural
Support for Programming Languages and Operating Systems. (ASPLOS
'IX)},
author = {Goldstein, Seth Copen},
address = {Cambridge, MA},
year = {2000},
month = {Nov},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Molecular Electronics,Reconfigurable Computing},
}
|
|
Tunable Fault Tolerance for Runtime Reconfigurable Architectures | pdf bib | |
Steven K. Sinha, Peter M. Kamarchik, and Seth Copen Goldstein.
In 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000),
pages 185–192, Apr 1990.
|
| @inproceedings{sinha-fccm00,
title = {Tunable Fault Tolerance for Runtime Reconfigurable
Architectures},
url = {http://www.cs.cmu.edu/~seth/papers/sinha-fccm00.pdf},
booktitle = {8th IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM 2000)},
author = {Sinha, Steven K. and Kamarchik, Peter M. and Goldstein,
Seth Copen},
abstract = {Fault tolerance is becoming an increasingly important
issue, especially in mission-critical applications where data
integrity is a paramount concern. Performance, however, remains a
large driving force in the market place. Runtime reconfigurable
hardware architectures have the power to balance fault tolerance
with performance, allowing the amount of fault tolerance to be
tuned at run-time. This paper describes a new built-in self-test
designed to run on, and take advantage of, runtime reconfigurable
architectures using the PipeRench architecture as a model. In
addition, this paper introduces a new metric by which a user can
set the desired fault tolerance of a runtime reconfigurable
device},
doi = {10.1109/FPGA.2000.903405},
year = {2000},
pages = {185-192},
isbn = {0-7695-0871-5},
address = {Napa Valley, CA},
month = {Apr},
keywords = {Fault And Defect Tolerance,PipeRench,Reconfigurable
Computing},
}
|
|
Tunable Fault Tolernace via Test and Reconfiguration | pdf bib | |
Shawn Blanton, Seth Copen Goldstein, and Herman Schmit.
In Digest of FastAbstracts of the 28th Annual International Symposium on Fault-Tolerant Computing,
pages 9–10, Jun 1990.
|
| @inproceedings{blanton-ftc98,
author = {Blanton, Shawn and Goldstein, Seth Copen and Schmit,
Herman},
title = {Tunable Fault Tolernace via Test and Reconfiguration},
booktitle = {Digest of FastAbstracts of the 28th Annual
International Symposium on Fault-Tolerant Computing},
year = {1998},
month = {Jun},
pages = {9--10},
keywords = {PipeRench, Fault and Defect Tolerance},
url = {http://www.cs.cmu.edu/~seth/papers/blanton-ftc98.pdf},
}
|
PipeRench |
|
Fault Tolerance in Run-time Reconfigurable Architectures | bib | |
Peter M. Kamarchik, Steven Sinha, and Seth Copen Goldstein.
In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '00),
Apr 1990.
|
| @inproceedings{KSS00,
author = {Kamarchik, Peter M. and Sinha, Steven and Goldstein, Seth
Copen},
title = {Fault Tolerance in Run-time Reconfigurable Architectures},
booktitle = {IEEE Symposium on FPGAs for Custom Computing Machines
(FCCM '00)},
year = {2000},
month = {Apr},
address = {Napa, CA},
keywords = {PipeRench, Fault and Defect Tolerance},
}
|
|
Pipeline Reconfigurable FPGAs | pdf bib | |
Herman Schmit, Seth Copen Goldstein, Srihari Cadambi, and Matthew Moe.
In Field-Programmable Custom Computing Technology: Architecture, Tools, and Applications,
1990.
|
| @incollection{schmit-fpcct00,
title = {Pipeline Reconfigurable FPGAs},
url = {http://www.cs.cmu.edu/~seth/papers/schmit-fpcct00.pdf},
booktitle = {Field-Programmable Custom Computing Technology:
Architecture, Tools, and Applications},
author = {Schmit, Herman and Goldstein, Seth Copen and Cadambi,
Srihari and Moe, Matthew},
year = {2000},
editor = {Arnold, Jeffrey and Luk, Wayne and Pocek, Ken},
publisher = {Kluwer Academic Publishers},
isbn = {0-7923-7803-2},
keywords = {PipeRench,Reconfigurable Computing},
}
|
|
Pipeline Reconfigurable FPGAs | pdf bib | |
Herman Schmit, Srihari Cadambi, Matthew Moe, and Seth Copen Goldstein.
Journal of VLSI Signal Processing Systems,
33(4):70–77, Apr 1990.
Also appeared as chapter in Field-Programmable Custom Computing Technology: Architecture, Tools, and Applications.
|
| @article{schmit-jvlsi00,
author = {Schmit, Herman and Cadambi, Srihari and Moe, Matthew and
Goldstein, Seth Copen},
title = {Pipeline Reconfigurable FPGAs},
journal = {Journal of VLSI Signal Processing Systems},
volume = {33},
month = {Apr},
year = {2000},
pages = {70-77},
abstract = {While reconfigurable computing promises to deliver
incomparable performance, it is still a marginal technology due
to the high cost of developing and upgrading applications.
Hardware virtualization can be used to significantly reduce both
these costs. In this paper we describe the benefits of hardware
virtualization, and show how it can be achieved using the
technique of pipeline reconfiguration. The result is PipeRench,
an architecture that supports robust compilation and provides
forward compatibility. Our preliminary performance analysis on
PipeRench predicts that it will outperform commercial FPGAs and
DSPs in both overall performance and in performance normalized
for silicon area over a broad range of problem sizes.},
number = {4},
url = {http://www.cs.cmu.edu/~seth/papers/schmit-jvlsi00.pdf},
doi = {},
also = {chapter in Field-Programmable Custom Computing Technology:
Architecture, Tools, and Applications},
keywords = {PipeRench,Reconfigurable Computing},
}
|
|
Tunable Fault Tolerance for Runtime Reconfigurable Architectures | pdf bib | |
Steven K. Sinha, Peter M. Kamarchik, and Seth Copen Goldstein.
In 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000),
pages 185–192, Apr 1990.
|
| @inproceedings{sinha-fccm00,
title = {Tunable Fault Tolerance for Runtime Reconfigurable
Architectures},
url = {http://www.cs.cmu.edu/~seth/papers/sinha-fccm00.pdf},
booktitle = {8th IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM 2000)},
author = {Sinha, Steven K. and Kamarchik, Peter M. and Goldstein,
Seth Copen},
abstract = {Fault tolerance is becoming an increasingly important
issue, especially in mission-critical applications where data
integrity is a paramount concern. Performance, however, remains a
large driving force in the market place. Runtime reconfigurable
hardware architectures have the power to balance fault tolerance
with performance, allowing the amount of fault tolerance to be
tuned at run-time. This paper describes a new built-in self-test
designed to run on, and take advantage of, runtime reconfigurable
architectures using the PipeRench architecture as a model. In
addition, this paper introduces a new metric by which a user can
set the desired fault tolerance of a runtime reconfigurable
device},
doi = {10.1109/FPGA.2000.903405},
year = {2000},
pages = {185-192},
isbn = {0-7695-0871-5},
address = {Napa Valley, CA},
month = {Apr},
keywords = {Fault And Defect Tolerance,PipeRench,Reconfigurable
Computing},
}
|
|
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations | pdf bib | |
Mihai Budiu, Majd Sakr, Kevin Walker, and Seth Copen Goldstein.
In Proceedings of the 2000 Europar Conference,
volume 1900, pages 969–979, Aug 1990.
Also appeared as CMU CS Technical Report, CMU-CS-00-141, October 2000..
|
| @inproceedings{budiu-europar00,
title = {{BitValue} Inference: Detecting and Exploiting Narrow
Bitwidth Computations},
author = {Budiu, Mihai and Sakr, Majd and Walker, Kevin and
Goldstein, Seth Copen},
booktitle = {Proceedings of the 2000 Europar Conference},
year = {2000},
volume = {1900},
pages = {969--979},
month = {Aug},
issn = {0302-9743},
series = {Lecture Notes in Computer Science},
publisher = {Springer Verlag},
address = {Munich, Germany},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-europar00.pdf},
also = {CMU CS Technical Report, CMU-CS-00-141, October 2000.},
abstract = {We present a compiler algorithm called BitValue, which
can discover both unused and constant bits in dusty-deck C
programs. BitValue uses forward and backward dataflow analyses,
generalizing constant-folding and dead-code detection at the
bit-level. This algorithm enables compiler optimizations which
target special processor architectures for computing on
non-standard bitwidths. Using this algorithm we show that up to
31\% of the computed bytes are thrown away (for programs from
SpecINT95 and Mediabench). A compiler for reconfigurable hardware
uses this algorithm to achieve substantial reductions (up to
20-fold) in the size of the synthesized circuits.},
keywords = {Spatial Computing,Reconfigurable
Computing,Phoenix,PipeRench,CAD},
}
|
|
PipeRench: A Reconfigurable Architecture and Compiler | pdf bib | |
Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matthew Moe, and R. Reed Taylor.
IEEE Computer,
33(4):70–77, Apr 1990.
|
| @article{goldstein-ieee00,
author = {Goldstein, Seth Copen and Schmit, Herman and Budiu, Mihai
and Cadambi, Srihari and Moe, Matthew and Taylor, R. Reed},
title = {{PipeRench}: A Reconfigurable Architecture and Compiler},
journal = {IEEE Computer},
year = {2000},
volume = {33},
number = {4},
month = {Apr},
pages = {70--77},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-ieee00.pdf},
abstract = {With the proliferation of highly specialized embedded
computer systems has come a diversification of workloads for
computing devices. General-purpose processors are struggling to
efficiently meet these applications' disparate needs, and custom
hardware is rarely feasible. According to the authors,
reconfigurable computing, which combines the flexibility of
general-purpose processors with the efficiency of custom
hardware, can provide the alternative. PipeRench and its
associated compiler comprise the authors' new architecture for
reconfigurable computing. Combined with a traditional digital
signal processor, microcontroller or general-purpose processor,
PipeRench can support a system's various computing needs without
requiring custom hardware. The authors describe the PipeRench
architecture and how it solves some of the pre-existing problems
with FPGA architectures, such as logic granularity, configuration
time, forward compatibility, hard constraints and compilation
time.},
keywords = {Reconfigurable Computing,PipeRench},
}
|
|
A High-Performance Flexible Architecture for Cryptography | pdf bib | |
R. Reed Taylor and Seth Copen Goldstein.
In Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems 1999 (CHES99),
pages 231–245, Aug 1990.
|
| @inproceedings{reed-ches99,
author = {Taylor, R. Reed and Goldstein, Seth Copen},
title = {A High-Performance Flexible Architecture for Cryptography},
booktitle = {Proceedings of the Workshop on Cryptographic Hardware
and Embedded Systems 1999 (CHES99)},
address = {Worcester, MA},
year = {1999},
pages = {231-245},
month = {Aug},
abstract = {Cryptographic algorithms are more efficiently
implemented in custom hardware than in software running on
general-purpose processors. However, systems which use hardware
implementations have significant drawbacks: they are unable to
respond to flaws discovered in the implemented algorithm or to
changes in standards. In this paper we show how reconfigurable
computing offers high performance yet flexible solutions for
cryptographic algorithms. We focus on PipeRench, a reconfigurable
fabric that supports implementations which can yield better than
custom-hardware performance and yet maintains all the flexibility
of software based systems. PipeRench is a pipelined
reconfigurable fabric which virtualizes hardware, enabling large
circuits to be run on limited physical hardware. We present
implementations for Crypton, IDEA, RC6, and Twofish on PipeRench
and an extension of PipeRench, PipeRench+. We also describe how
various proposed AES algorithms could be implemented on
PipeRench. PipeRench achieves speedups of between 2x and 12x over
conventional processors.},
url = {http://www.cs.cmu.edu/~seth/papers/reed-ches99.pdf},
keywords = {PipeRench,Reconfigurable Computing},
}
|
|
Fast Compilation for Pipelined Reconfigurable Fabrics | pdf bib | |
Mihai Budiu and Seth Copen Goldstein.
In Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays (FPGA '99),
pages 195–205, Feb 1990.
|
| @inproceedings{budiu-fpga99,
author = {Budiu, Mihai and Goldstein, Seth Copen},
title = {Fast Compilation for Pipelined Reconfigurable Fabrics},
booktitle = {Proceedings of the 1999 ACM/SIGDA Seventh International
Symposium on Field Programmable Gate Arrays (FPGA '99)},
month = {Feb},
year = {1999},
pages = {195-205},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-fpga99.pdf},
abstract = {In this paper we describe a compiler which quickly
synthesizes high quality pipelined datapaths for pipelined
reconfigurable devices. The compiler uses the same internal
representation to perform synthesis, module generation,
optimization, and place and route. The core of the compiler is a
linear time place and route algorithm more than two orders of
magnitude faster than traditional CAD tools. The key behind our
approach is that we never backtrack, rip-up, or re-route.
Instead, the graph representing the computation is preprocessed
to guarantee routability by inserting lazy noops. The
preprocessing steps provides enough information to make a greedy
strategy feasible. The compilation speed is approximately 3000
bit-operations/second (on a PII/400Mhz) for a wide range of
applications. The hardware utilization averages 60\% on the
target device, PipeRench.},
keywords = {Reconfigurable Computing,PipeRench,Place and Route},
}
|
|
PipeRench: a Coprocessor for Streaming Multimedia Acceleration | pdf bib | |
Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, and Ronald Laufer.
In Proceedings of the 26th International Symposium on Computer Architecture (ISCA),
pages 28–39, May 1990.
|
| @inproceedings{goldstein-isca99,
author = {Goldstein, Seth Copen and Schmit, Herman and Moe, Matthew
and Budiu, Mihai and Cadambi, Srihari and Taylor, R. Reed and
Laufer, Ronald},
title = {{PipeRench}: a Coprocessor for Streaming Multimedia
Acceleration},
booktitle = {Proceedings of the 26th International Symposium on
Computer Architecture (ISCA)},
month = {May},
year = {1999},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca99.pdf},
pages = {28--39},
abstract = {Future computing workloads will emphasize an
architecture's ability to perform relatively simple calculations
on massive quantities of mixed-width data. This paper describes a
novel reconfigurable fabric architecture, PipeRench, optimized to
accelerate these types of computations. PipeRench enables fast,
robust compilers, supports forward compatibility, and virtualizes
configurations, thus removing the fixed size constraint present
in other fabrics. For the first time we explore how the bit-width
of processing elements affects performance and show how the
PipeRench architecture has been optimized to balance the needs of
the compiler against the realities of silicon. Finally, we
demonstrate extreme performance speedup on certain computing
kernels (up to 190x versus a modern RISC processor), and analyze
how this acceleration translates to application speedup.},
address = {Atlanta, GA},
keywords = {Reconfigurable Computing,PipeRench},
}
|
|
Tunable Fault Tolernace via Test and Reconfiguration | pdf bib | |
Shawn Blanton, Seth Copen Goldstein, and Herman Schmit.
In Digest of FastAbstracts of the 28th Annual International Symposium on Fault-Tolerant Computing,
pages 9–10, Jun 1990.
|
| @inproceedings{blanton-ftc98,
author = {Blanton, Shawn and Goldstein, Seth Copen and Schmit,
Herman},
title = {Tunable Fault Tolernace via Test and Reconfiguration},
booktitle = {Digest of FastAbstracts of the 28th Annual
International Symposium on Fault-Tolerant Computing},
year = {1998},
month = {Jun},
pages = {9--10},
keywords = {PipeRench, Fault and Defect Tolerance},
url = {http://www.cs.cmu.edu/~seth/papers/blanton-ftc98.pdf},
}
|
|
Characterization and Parameterization of a Pipeline Reconfigurable FGPA | pdf bib | |
Matthew Moe, Herman Schmit, and Seth Copen Goldstein.
In 6th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98),
pages 294–295, Apr 1990.
|
| @inproceedings{moe-fccm98,
author = {Moe, Matthew and Schmit, Herman and Goldstein, Seth
Copen},
title = {{Characterization and Parameterization of a Pipeline
Reconfigurable {FGPA}}},
booktitle = {6th Annual IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM '98)},
month = {Apr},
address = {Napa, CA},
year = {1998},
pages = {294--295},
note = {poster session 3},
keywords = {PipeRench, Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/moe-fccm98.pdf},
}
|
|
Managing pipeline-reconfigurable FPGAs | pdf bib | |
Srihari Cadambi, J. Weener, Seth Copen Goldstein, Herman Schmit, and Donald E Thomas.
In Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays,
pages 55–64, Feb 1990.
|
| @inproceedings{cadambi-fpga98,
author = {Cadambi, Srihari and Weener, J. and Goldstein, Seth Copen
and Schmit, Herman and Thomas, Donald E},
title = {{Managing pipeline-reconfigurable FPGAs}},
booktitle = {Proceedings of the 1998 ACM/SIGDA Sixth International
Symposium on Field Programmable Gate Arrays},
year = {1998},
month = {Feb},
pages = {55--64},
address = {Monterey, CA},
abstract = {While reconfigurable computing promises to deliver
incomparable performance, it is still a marginal technology due
to the high cost of developing and upgrading applications.
Hardware virtualization can be used to significantly reduce both
these costs. In this paper we describe the benefits of hardware
virtualization, and show how it can be acheived using a
combination of pipeline reconfiguration and run-time scheduling
of both configuration streams and data streams. The result is
PipeRench, an architecture that supports robust compilation and
provides forward compatibility. Our preliminary performance
analysis predicts that PipeRench will outperform commercial FPGAs
and DSPs in both overall performance and in performance per
mm$^2$.},
keywords = {PipeRench, Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpga98.pdf},
}
|
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