MolSpice: Designing Molecular Logic Circuits

@article{lincoln-tnano05,
  title = {Nonphotolithographic Nanoscale Memory Density Prospects},
  abstract = {Technologies are now emerging to construct
     molecular-scale electronic wires and switches using bottom-up
     self-assembly. This opens the possibility of constructing
     nanoscale circuits and memories where active devices are just a
     few nanometers square and wire pitches may be on the order of ten
     nanometers. The features can be defined at this scale without
     using photolithography. The available assembly techniques have
     relatively high defect rates compared to conventional
     lithographic integrated circuits and can only produce very
     regular structures. Nonetheless, with proper memory organization,
     it is reasonable to expect these technologies to provide memory
     densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
     power requirements under 0.6 W/Tb/s for random read operations.},
  url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
  journal = {IEEE Transactions on Nanotechnology},
  author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
     and Lincoln, Patrick},
  year = {2005},
  month = {Mar},
  volume = {4},
  issue = {2},
  pages = {215-228},
  keywords = {Fault and Defect Tolerance, electronic nanotechnology,
     memory density, memory organization, molecular electronics},
  doi = {10.1109/TNANO.2004.837849},
}

@inproceedings{goldstein-iccad05,
  title = {The impact of the nanoscale on computing systems},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-iccad05.pdf},
  booktitle = {IEEE/ACM International Conference on Computer-Aided
     Design, 2005 (ICCAD 2005)},
  author = {Goldstein, Seth Copen},
  year = {2005},
  pages = {655-661},
  address = {San Jose, CA},
  month = {Nov},
  keywords = {Electronic Nanotechnology,molecular electronics},
}

@incollection{mishra-nqmc04,
  title = {Defect Tolerance at the End of the Roadmap},
  booktitle = {Nano, Quantum and Molecular Computing: Implications to
     High Level Design and Validation},
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  year = {2004},
  editor = {Sandeep K. Shukla and R. Iris Bahar},
  publisher = {Kluwer Academic Publishers},
  isbn = {1-4020-80670},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Reconfigurable Computing,Phoenix,molecular
     electronics},
}

@misc{patent06,
  author = {Goldstein, Seth Copen and Rosewater, Daniel L.},
  title = {Methods of chemically assembled electronic nanotechnology
     circuit fabrication},
  howpublished = {United States Patent No. 7,064,000. Issued June 20,
     2006},
  month = {Jul},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/patent06.pdf},
  keywords = {Molecular Electronics,Two-Terminal Devices},
  abstract = {Chemically assembled electronic nanotechnology (CAEN)
     provides an alternative to using Complementary Metal Oxide
     Semiconductor (CMOS) for constructing circuits with feature sizes
     in the tens of nanometers. A molecular latch and a method using
     the latch that enables it to act as a state holding device,
     perform voltage restoration, and to provide I/O isolation is
     disclosed.},
  url = {http://www.cs.cmu.edu/~seth/papers/patent06.pdf},
}

@incollection{goldstein-mn03,
  title = {Molecules, Gates, Circuits, Computer},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
  booktitle = {Molecular Nanoelectronics},
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  year = {2003},
  editor = {Mark A. Reed and Takhee Lee},
  publisher = {American Scientific Publishers},
  address = {Stevenson Ranch, CA},
  month = {Jan},
  isbn = {1-588883-006-3},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Reconfigurable Computing,Spatial
     Computing,electronic nanotechnology,molecular electronics},
}

@inproceedings{shukla-hldvt03,
  title = {Nano, Quantum, and Molecular Computing: Are We Ready for
     the Validation and Test Challenges},
  url = {http://www.cs.cmu.edu/~seth/papers/shukla-hldvt03.pdf},
  talk = {http://www.cs.cmu.edu/~seth/hldvt03-goldstein.pdf},
  booktitle = {Eighth IEEE International High-Level Design Validation
     and Test Workshop},
  author = {Shukla, Sandeep K. and Karri, Ramesh and Goldstein, Seth
     Copen and Brewer, Forest and Banerjee, Kaustav and Basu, Sankar},
  year = {2003},
  month = {Nov},
  pages = {307},
  address = {San Francisco, CA},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,molecular electronics},
}

@inproceedings{isscc02,
  author = {Rosewater, Dan and Goldstein, Seth Copen},
  title = {Digital Logic Using Molecular Electronics},
  booktitle = {IEEE International Solid-State Circuits Conference
     (ISSCC)},
  year = {2002},
  month = {Feb},
  address = {San Francisco, CA},
  keywords = {Electronic Nanotechnology,Molecular
     Electronics,Two-Terminal Devices},
  url = {http://www.cs.cmu.edu/~seth/papers/isscc02.pdf},
}

@inproceedings{butts-iccad02,
  title = {Molecular electronics: devices, systems and tools for
     gigagate,gigabit chips},
  url = {http://www.cs.cmu.edu/~seth/papers/butts-iccad02.pdf},
  doi = {http://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167569},
  booktitle = {International Conference on Computer-Aided Design (
     ICCAD '02)},
  author = {Butts, Michael and DeHon, Andre and Goldstein, Seth
     Copen},
  abstract = {New electronics technologies are emerging which may
     carry us beyond the limits of lithographic processing down to
     molecular-scale feature sizes. Devices and interconnects can be
     made from a variety of molecules and materials including bistable
     and switchable organic molecules, carbon nanotubes, and,
     single-crystal semiconductor nanowires. They can be
     self-assembled into organized structures and attached onto
     lithographic substrates. This tutorial reviews emerging
     molecular-scale electronics technology for CAD and system
     designers and highlights where ICCAD research can help support
     this technology.},
  address = {San Jose, CA},
  year = {2002},
  pages = {433-440},
  note = {invited tutorial at},
  month = {Nov},
  keywords = {Electronic Nanotechnology,Reconfigurable
     Computing,molecular electronics},
}

@misc{patent04,
  author = {Goldstein, Seth Copen and Rosewater, Daniel L.},
  title = {Molecular scale latch and associated clocking scheme to
     provide gain, memory and I/O isolation},
  howpublished = {United States Patent No. 6,777,982. Issued August
     17, 2004},
  month = {Apr},
  url = {http://www.cs.cmu.edu/~seth/papers/patent04.pdf},
  year = {2002},
  keywords = {Molecular Electronics,Two-Terminal Devices},
  abstract = {Chemically assembled electronic nanotechnology (CAEN)
     provides an alternative to using Complementary Metal Oxide
     Semiconductor (CMOS) for constructing circuits with feature sizes
     in the tens of nanometers. A molecular latch and a method using
     the latch that enables it to act as a state holding device,
     perform voltage restoration, and to provide I/O isolation is
     disclosed.},
  url = {http://www.cs.cmu.edu/~seth/papers/patent04.pdf},
}

@inproceedings{goldstein-foresight01,
  author = {Goldstein, Seth Copen and Ellenbogen, James and Almassiam,
     David and Brown, Matt and Cannarsa, Mark and Klein, Jesse and
     Schell, Schuyler and Washburn, Geoff and Ziegler, Matthew M},
  title = {MolSpice: Designing Molecular Logic Circuits},
  booktitle = {Ninth Foresight Conference on Molecular
     Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-foresight01.pdf},
  year = {2001},
  month = {Nov},
  address = {Santa Clara, CA},
  keywords = {Electronic Nanotechnology, Molecular Electronics, CAD},
}

@inproceedings{goldstein-asplos00,
  title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
  booktitle = {The 10th International Conference on Architectural
     Support for Programming Languages and Operating Systems. (ASPLOS
     'IX)},
  author = {Goldstein, Seth Copen},
  address = {Cambridge, MA},
  year = {2000},
  month = {Nov},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Molecular Electronics,Reconfigurable Computing},
}

@inproceedings{venkataramani-codes08,
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM/IFIP International Conference on
     Hardware/Software Codesign and System Synthesis {(CODES-ISSS)}},
  year = {2008},
  address = {Atlanta, GE},
  month = {Oct},
  keywords = {Asychronous Circuits, CAD, Global Critical Path},
  title = {Slack Analysis in the System Design Loop},
  talk = {http://www.cs.cmu.edu/~seth/papers/talk-venkataramani-codes08.pdf},
  pages = {231--236},
}

@inproceedings{chelcea-async07,
  author = {Chelcea, Tiberiu and Venkataramani, Girish and Goldstein,
     Seth Copen},
  title = {Area Optimizations for Dual-Rail Circuits Using
     Relative-Timing Analysis},
  booktitle = {Proceedings of the 13th IEEE International Symposium on
     Asynchronous Circuits and Systems},
  year = {2007},
  address = {Berkeley, CA},
  month = {Mar},
  pages = {117--128},
  abstract = {Future deep sub-micron technologies will be
     characterized by large parametric variations, which could make
     asynchronous design an attractive solution for use on large
     scale. However, the investment in asynchronous CAD tools does not
     approach that in synchronous ones. Even when asynchronous tools
     leverage existing synchronous toolflows, they introduce large
     area and speed overheads. This paper proposes several heuristic
     and optimal algorithms, based on timing interval analysis, for
     improving existing asynchronous CAD solutions by optimizing area.
     The optimized circuits are 2.4 times smaller for an optimal
     algorithm and 1.8 times smaller for a heuristic one than the
     existing solutions. The optimized circuits are also shown to be
     resilient to large parametric variations, yielding better
     average-case latencies than their synchronous counterparts.},
  url = {http://www.cs.cmu.edu/~seth/papers/chelcea-async07.pdf},
  keywords = {Asychronous Circuits, CAD},
}

@inproceedings{dac07-gcp,
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  title = {Global Critical Path: A Tool for System-Level Timing
     Analysis},
  booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
     Conference},
  year = {2007},
  month = {Jun},
  address = {San Diego, CA},
  pages = {783--786},
  abstract = {An effective method for focusing optimization effort on
     the most important parts of a design is to examine those elements
     on the critical path. Traditionally, the critical path is defined
     at the RTL level, as the longest path in the combinational logic
     between clocked reisters. In this paper, we present a
     system-level timing analysis technique to define the concept of a
     Global Critical Path (GCP), for predicting system-level
     performance. We show how the GCP can be used as a theoretical and
     practical tool for understanding, summarizing and optimizing the
     behavior of highly concurrent self-timed circuits. We formally
     define the GCP and show how it can be constructed using a
     discrete event model and hardware profiling techniques. The GCP
     provides valuable insight into the control-path behavior of
     circuits and in finding system-level bottlenecks. We have
     incorporated the GCP construction and analysis framework into a
     high-level synthesis and simulation toolchain, thus enabling
     complete automation in modeling, analysis and optimization.},
  url = {http://www.cs.cmu.edu/~seth/papers/dac07-gcp.pdf},
  keywords = {Asychronous Circuits, CAD, Global Critical Path, System
     modeling, Hardware profiling},
}

@inproceedings{venkataramani-iccad07,
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  title = {Operation Chaining Asynchronous Pipelined Circuits},
  booktitle = {ICCAD},
  abstract = {We define operation chaining (op-chaining) as an
     optimization problem to determine the optimal pipeline depth for
     balancing performance against energy demands in pipelined
     asynchronous designs. Since there are no clock period
     requirements, asynchronous pipeline stages can have non-uniform
     latencies. We exploit this fact to coalesce several stages
     together thereby saving power and area due to the elimination of
     control-path resources from the pipeline. The trade-off is
     potentially reduced pipeline parallelism. 
In this paper, we
     formally define this optimization as a graph covering problem,
     which finds sub-graphs that will be synthesized as an opchained
     pipeline stage. We then define the solution space for provably
     correct solutions and present an algorithm to efficiently search
     this space. The search technique partitions the graph based on
     post-dominator relationships to find sub-graphs that are
     potential op-chain candidates. We use knowledge of the Global
     Critical Path (GCP) [13] to evaluate the performance impact of
     accepting a candidate sub-graph and formulate a heuristic cost
     function to model this trade-off. The algorithm has a
     quadratic-time complexity in the size of the dataflow graph. We
     have implemented this algorithm within an automated asynchronous
     synthesis toolchain [12]. Experimental evidence from applying the
     algorithm on several media processing kernels reveals that the
     average energy-delay and energy-delay-area products improve by
     about 1.4x and 1.8x respectively, with a maximum improvement of
     5x and 18x.},
  month = {Nov},
  year = {2007},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iccad07.pdf},
  keywords = {Asychronous Circuits, CAD, Global Critical Path},
}

@inproceedings{venkataramani-iccad06,
  title = {Leveraging Protocol Knowledge in Slack Matching},
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM International Conference on Computer-Aided
     Design (ICCAD)},
  year = {2006},
  address = {San Jose, CA},
  month = {Nov},
  abstract = {{Stalls, due to mis-matches in communication rates, are
     a major performance obstacle in pipelined circuits. If the rate
     of data production is faster than the rate of consumption, the
     resulting design performs slower than when the communication rate
     is matched. This can be remedied by inserting pipeline buffers
     (to temporarily hold data), allowing the producer to proceed if
     the consumer is not ready to accept data. The problem of deciding
     which channels need these buffers (and how many) for an arbitrary
     communication profile is called the slack matching problem; the
     optimal solution to this problem has been shown to be
     NP-complete. \par In this paper, we present a heuristic that uses
     knowledge of the communication protocol to explicitly model these
     bottlenecks, and an iterative algorithm to progressively remove
     these bottlenecks by inserting buffers. We apply this algorithm
     to asynchronous circuits, and show that it naturally handles
     large designs with arbitrarily cyclic and acyclic topologies,
     which exhibit various types of control choice. The heuristic is
     efficient, achieving linear time complexity in practice, and
     produces solutions that (a) achieve up to 60\% performance
     speedup on large media processing kernels, and (b) can either be
     verified to be optimal, or the approximation margin can be
     bounded. }},
  keywords = {Asychronous Circuits, Spatial Computing, CAD, Global
     Critical Path},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iccad06.pdf},
}

@techreport{venkataramani-tr06,
  author = {Venkataramani, Girish and Chelcea, Tiberiu and Budiu,
     Mihai and Goldstein, Seth Copen},
  title = {Modeling the Global Critical Path in Concurrent Systems},
  institution = {Carnegie Mellon University},
  year = {2006},
  number = {CMU-CS-06-144},
  month = {Aug},
  abstract = {We show how the global critical path can be used as a
     practical tool for understanding, optimizing and summarizing the
     behavior of highly concurrent self-timed circuits. Traditionally,
     critical path analysis has been applied to DAGs, and thus was
     constrained to combinatorial sub-circuits. We formally define the
     global critical path (GCP) and show how it can be constructed
     using only local information that is automatically derived
     directly from the circuit. We introduce a form of Production
     Rules, which can accurately determine the GCP for a given input
     vector, even for modules which exhibit choice and early
     termination. \par The GCP provides valuable insight into the
     control behavior of the application, which help in formulating
     new optimizations and re-formulating existing ones to use the GCP
     knowledge. We have constructed a fully automated framework for
     GCP detection and analysis, and have incorporated this framework
     into a high-level synthesis tool-chain. We demonstrate the
     effectiveness of the GCP framework by re-formulating two
     traditional CAD optimizations to use the GCP, yielding efficient
     algorithms which improve circuit power (by up to 9\%) and
     performance (by up to 60\%) in our experiments.},
  keywords = {Asychronous Circuits, Spatial Computing,CAD, Global
     Critical Path},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-tr06.pdf},
}

@inproceedings{venkataramani-isss05,
  title = {SOMA: A Tool for Synthesizing and Optimizing Memory
     Accesses in ASICs},
  author = {Venkataramani, Girish and Bjerregaard, Tobias and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM/IFIP International Conference on
     Hardware/Software Codesign and System Synthesis (CODES-ISSS)},
  year = {2005},
  isbn = {1-59593-161-9},
  pages = {231-236},
  address = {Jersey City, NJ, USA},
  month = {Sep},
  abstract = {Arbitrary memory dependencies and variable latency
     memory systems are major obstacles to the synthesis of
     large-scale ASIC systems in high-level synthesis. This paper
     presents SOMA, a synthesis framework for constructing Memory
     Access Network (MAN) architectures that inherently enforce memory
     consistency in the presence of dynamic memory access
     dependencies. A fundamental bottleneck in any such network is
     arbitrating between concurrent accesses to a shared memory
     resource. To alleviate this bottleneck, SOMA uses an
     application-specific concurrency analysis technique to predict
     the dynamic memory parallelism profile of the application. This
     is then used to customize the MAN architecture. Depending on the
     parallelism profile, the MAN may be optimized for latency,
     throughput or both. The optimized MAN is automatically
     synthesized into gate-level structural Verilog using a flexible
     library of network building blocks. SOMA has been successfully
     integrated into an automated C-to-hardware synthesis flow, which
     generates standard cell circuits from unrestricted ANSI-C
     programs. Post-layout experiments demonstrate that application
     specific MAN construction significantly improves power and
     performance.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix,
     CAD,Compilers:Memory Optimizations},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-isss05.pdf},
}

@inproceedings{budiu-async04,
  title = {Translating ANSI C to Asynchronous Circuits},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
  booktitle = {10th IEEE International Symposium on Asynchronous
     Circuits and Systems (ASYNC '04)},
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  address = {Crete, Greece},
  year = {2004},
  month = {Apr},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
     Computing},
}

@inproceedings{venkataramani-iwls04,
  title = {{C} to Asynchronous Dataflow Circuits: An End-to-End
     Toolflow},
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  booktitle = {IEEE 13th International Workshop on Logic Synthesis
     (IWLS)},
  address = {Temecula, CA},
  month = {Jun},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iwls04.pdf},
  abstract = {We present a complete toolflow that translates ANSI-C
     programs into asynchronous circuits. The toolflow is built around
     a compiler that converts C into a functional dataflow
     intermediate representation, exposing instruction-level, pipeline
     and memory parallelism. The compiler performs optimizations and
     converts the intermediate representation into pipelined
     asynchronous circuits, with no centralized controllers. In the
     resulting circuits, control is distributed, communication is
     achieved through local wires, and arbitration for datapath
     resources is unnecessary. Circuits automatically synthesized from
     Mediabench kernels exhibit substantially better energy-delay than
     either single-issue processors or aggressive superscalar cores.},
  keywords = {Asychronous Circuits,Spatial Computing,Phoenix,CAD},
}

@incollection{goldstein-mn03,
  title = {Molecules, Gates, Circuits, Computer},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
  booktitle = {Molecular Nanoelectronics},
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  year = {2003},
  editor = {Mark A. Reed and Takhee Lee},
  publisher = {American Scientific Publishers},
  address = {Stevenson Ranch, CA},
  month = {Jan},
  isbn = {1-588883-006-3},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Reconfigurable Computing,Spatial
     Computing,electronic nanotechnology,molecular electronics},
}

@inproceedings{goldstein-foresight01,
  author = {Goldstein, Seth Copen and Ellenbogen, James and Almassiam,
     David and Brown, Matt and Cannarsa, Mark and Klein, Jesse and
     Schell, Schuyler and Washburn, Geoff and Ziegler, Matthew M},
  title = {MolSpice: Designing Molecular Logic Circuits},
  booktitle = {Ninth Foresight Conference on Molecular
     Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-foresight01.pdf},
  year = {2001},
  month = {Nov},
  address = {Santa Clara, CA},
  keywords = {Electronic Nanotechnology, Molecular Electronics, CAD},
}

@inproceedings{cadambi-fpl01,
  title = {Static Profile-driven Compilation for FPGAs},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpl01.pdf},
  booktitle = {Proceedings of the 11th International Conference on
     Field-Programmable Logic and Applications},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  address = {Belfast, Northern Ireland},
  year = {2001},
  month = {Aug},
  keywords = {CAD,Reconfigurable Computing},
}

@techreport{budiu-tr00,
  title = {BitValue Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr00.pdf},
  booktitle = {CMU CS Technical Report, CMU-CS-00-141},
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  institution = {Carnegie Mellon University},
  year = {2000},
  month = {Jun},
  see = {budiu-europar00},
  keywords = {CAD,Compilers:CASH,Reconfigurable Computing},
}

@inproceedings{cadambi-iccd00,
  title = {Efficient Place and Route for Pipeline Reconfigurable
     Architectures},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-iccd00.pdf},
  booktitle = {ICCD '00},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  address = {Austin, TX},
  year = {2000},
  month = {Sep},
  keywords = {CAD,Place and Route},
}

@inproceedings{budiu-europar00,
  title = {{BitValue} Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  author = {Budiu, Mihai and Sakr, Majd and Walker, Kevin and
     Goldstein, Seth Copen},
  booktitle = {Proceedings of the 2000 Europar Conference},
  year = {2000},
  volume = {1900},
  pages = {969--979},
  month = {Aug},
  issn = {0302-9743},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer Verlag},
  address = {Munich, Germany},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-europar00.pdf},
  also = {CMU CS Technical Report, CMU-CS-00-141, October 2000.},
  abstract = {We present a compiler algorithm called BitValue, which
     can discover both unused and constant bits in dusty-deck C
     programs. BitValue uses forward and backward dataflow analyses,
     generalizing constant-folding and dead-code detection at the
     bit-level. This algorithm enables compiler optimizations which
     target special processor architectures for computing on
     non-standard bitwidths. Using this algorithm we show that up to
     31\% of the computed bytes are thrown away (for programs from
     SpecINT95 and Mediabench). A compiler for reconfigurable hardware
     uses this algorithm to achieve substantial reductions (up to
     20-fold) in the size of the synthesized circuits.},
  keywords = {Spatial Computing,Reconfigurable
     Computing,Phoenix,PipeRench,CAD},
}

@inproceedings{cadambi-fccm99,
  title = {CPR: A Configuration Profiling Tool},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fccm99.pdf},
  booktitle = {7th Annual IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM '99)},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  year = {1999},
  pages = {104},
  address = {Napa Valley, CA},
  month = {Apr},
  keywords = {CAD,Reconfigurable Computing,Place And Route},
}

@article{lincoln-tnano05,
  title = {Nonphotolithographic Nanoscale Memory Density Prospects},
  abstract = {Technologies are now emerging to construct
     molecular-scale electronic wires and switches using bottom-up
     self-assembly. This opens the possibility of constructing
     nanoscale circuits and memories where active devices are just a
     few nanometers square and wire pitches may be on the order of ten
     nanometers. The features can be defined at this scale without
     using photolithography. The available assembly techniques have
     relatively high defect rates compared to conventional
     lithographic integrated circuits and can only produce very
     regular structures. Nonetheless, with proper memory organization,
     it is reasonable to expect these technologies to provide memory
     densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
     power requirements under 0.6 W/Tb/s for random read operations.},
  url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
  journal = {IEEE Transactions on Nanotechnology},
  author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
     and Lincoln, Patrick},
  year = {2005},
  month = {Mar},
  volume = {4},
  issue = {2},
  pages = {215-228},
  keywords = {Fault and Defect Tolerance, electronic nanotechnology,
     memory density, memory organization, molecular electronics},
  doi = {10.1109/TNANO.2004.837849},
}

@inproceedings{goldstein-iccad05,
  title = {The impact of the nanoscale on computing systems},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-iccad05.pdf},
  booktitle = {IEEE/ACM International Conference on Computer-Aided
     Design, 2005 (ICCAD 2005)},
  author = {Goldstein, Seth Copen},
  year = {2005},
  pages = {655-661},
  address = {San Jose, CA},
  month = {Nov},
  keywords = {Electronic Nanotechnology,molecular electronics},
}

@inproceedings{beckett-iscas05,
  title = {Why area might reduce power in nanoscale CMOS},
  url = {http://www.cs.cmu.edu/~seth/papers/beckett-iscas05.pdf},
  booktitle = {IEEE International Symposium on Circuits and Systems,
     2005, (ISCAS 2005)},
  author = {Beckett, Paul and Goldstein, Seth Copen},
  year = {2005},
  pages = {2329-2332},
  volume = {3},
  month = {May},
  address = {Kobe, Japan},
  abstract = {In this paper we explore the relationship between power
     and area. By exploiting parallelism (and thus using more area)
     one can reduce the switching frequency allowing a reduction in
     VDD which results in a reduction in power. Under a scaling regime
     which allows threshold voltage to increase as VDD decreases we
     find that dynamic and subthreshold power loss in CMOS exhibit a
     dependence on area proportional to A^((\sigma^-3)/\sigma) while
     gate leakage power proportional to A^((\sigma^-6)/\sigma) and
     short circuit power A^((\sigma^-6)/\sigma). Thus, with the large
     number of devices at our disposal we can exploit techniques such
     as spatial computing--tailoring the program directly to the
     hardware--to overcome the negative effects of scaling. The value
     of s describes the effectiveness of the technique for a
     particular circuit and/or algorithm--for circuits that exhibit a
     value of \sigma <= 3, power will be a constant or reducing
     function of area. We briefly speculate on how \sigma might be
     influenced by a move to nanoscale technology.},
  keywords = {Electronic Nanotechnology,Power,Energy},
}

@inproceedings{goldstein04-ersa04,
  author = {Goldstein, Seth Copen},
  title = {Computing Without Processors},
  booktitle = {International Conference on Engineering of
     Reconfigurable Systems and Algorithms (ERSA'04)},
  abstract = {The continuation of the remarkable exponential increases
     in processing power over the recent past faces imminent
     challenges due in part rising cost of design and manufacturing
     and the physics of deep-submicron semiconductor devices. In this
     talk we will discuss a promising alternative to ever more complex
     processors, application specific hardware (ASH). The ASH model is
     based on compiling high-level programs directly into circuits,
     which can either be fabricated as ASICs or more reasonably
     converted in configurations for reconfigurable devices. We will
     discuss the challenges involved in compiling sequential
     programming languages into circuits and the challenges in
     implementing those circuits in a scalable and power efficient
     manner.},
  address = {Las Vegas, NV},
  month = {Jun},
  year = {2004},
  pages = {29--32},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology,
     Fault and Defect Tolerance},
}

@incollection{mishra-nqmc04,
  title = {Defect Tolerance at the End of the Roadmap},
  booktitle = {Nano, Quantum and Molecular Computing: Implications to
     High Level Design and Validation},
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  year = {2004},
  editor = {Sandeep K. Shukla and R. Iris Bahar},
  publisher = {Kluwer Academic Publishers},
  isbn = {1-4020-80670},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Reconfigurable Computing,Phoenix,molecular
     electronics},
}

@inproceedings{goldstein-gomac04,
  title = {The Challenges and Opportunities of Nanoelectronics},
  author = {Goldstein, Seth Copen},
  booktitle = {Proceedings of Government Microcircuit Applications and
     Critical Technology Conference (GOMAC Tech 04)},
  year = {2004},
  address = {Monterey, CA},
  keywords = {Electronic Nanotechnology},
  month = {Mar},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-gomac04.pdf},
}

@inproceedings{budiu-async04,
  title = {Translating ANSI C to Asynchronous Circuits},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
  booktitle = {10th IEEE International Symposium on Asynchronous
     Circuits and Systems (ASYNC '04)},
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  address = {Crete, Greece},
  year = {2004},
  month = {Apr},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
     Computing},
}

@inproceedings{goldstein-inano03,
  title = {Models and Abstractions for Nanoelectronics},
  booktitle = {Third IEEE Conference on Nanotechnology (IEEE-NANO
     2003)},
  author = {Goldstein, Seth Copen and Zhu, Y},
  address = {San Francisco, CA},
  year = {2003},
  month = {Aug},
  keywords = {Electronic Nanotechnology},
}

@article{mircea-ieee03,
  title = {Molecular Electronics: From Devices and Interconnect to
     Circuits and Architecture},
  author = {Stan, Mircea R and Franzon, Paul D and Goldstein, Seth
     Copen and Lach, John C and Ziegler, Matthew M},
  journal = {Proceedings of the IEEE},
  year = {2003},
  volume = {91},
  number = {11},
  month = {Nov},
  keywords = {Electronic Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/mircea-ieee03.pdf},
}

@incollection{goldstein-mn03,
  title = {Molecules, Gates, Circuits, Computer},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
  booktitle = {Molecular Nanoelectronics},
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  year = {2003},
  editor = {Mark A. Reed and Takhee Lee},
  publisher = {American Scientific Publishers},
  address = {Stevenson Ranch, CA},
  month = {Jan},
  isbn = {1-588883-006-3},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Reconfigurable Computing,Spatial
     Computing,electronic nanotechnology,molecular electronics},
}

@inproceedings{shukla-hldvt03,
  title = {Nano, Quantum, and Molecular Computing: Are We Ready for
     the Validation and Test Challenges},
  url = {http://www.cs.cmu.edu/~seth/papers/shukla-hldvt03.pdf},
  talk = {http://www.cs.cmu.edu/~seth/hldvt03-goldstein.pdf},
  booktitle = {Eighth IEEE International High-Level Design Validation
     and Test Workshop},
  author = {Shukla, Sandeep K. and Karri, Ramesh and Goldstein, Seth
     Copen and Brewer, Forest and Banerjee, Kaustav and Basu, Sankar},
  year = {2003},
  month = {Nov},
  pages = {307},
  address = {San Francisco, CA},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,molecular electronics},
}

@inproceedings{goldstein-asap03,
  title = {Reconfigurable Computing and Electronic Nanotechnology},
  author = {Goldstein, Seth Copen and Budiu, Mihai and Mishra, Mahim
     and Venkataramani, Girish},
  booktitle = {Proceedings of the {IEEE} 14th International Conference
     on Application-specific Systems, Architectures and Processors
     ({ASAP} 2003)},
  year = {2003},
  address = {The Hague, Netherlands},
  month = {Jun},
  note = {Invited paper},
  pages = {132-143},
  abstract = {In this paper we examine the opportunities brought about
     by recent progress in electronic nanotechnology and describe the
     methods needed to harness them for building a new computer
     architecture. In this process we decompose some traditional
     abstractions, such as the transistor, into fine-grain pieces,
     such as signal restoration and input-output isolation. We also
     show how we can forgo the extreme reliability of CMOS circuits
     for low-cost chemical self-assembly at the expense of large
     manufacturing defect densities. We discuss advanced testing
     methods which can be used to recover perfect functionality from
     unreliable parts. We proceed to show how the molecular switch,
     the regularity of the circuits created by self-assembly and the
     high defect densities logically require the use of reconfigurable
     hardware as a basic building block for hardware design. We then
     capitalize on the convergence of compilation and hardware
     synthesis (which takes place when programming reconfigurable
     hardware) to propose the complete elimination of the
     instruction-set architecture from the system architecture, and
     the synthesis of asynchronous dataflow machines directly from
     high-level programming languages, such as C. We discuss in some
     detail a scalable compilation system that perform this task.},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asap03.pdf},
}

@inproceedings{goldstein-hldvt03,
  title = {Reconfigurable Nanoelectronics and Defect Tolerance},
  author = {Goldstein, Seth Copen},
  booktitle = {Proceedings of High-level design, verification, and
     test},
  year = {2003},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology,
     Fault and Defect Tolerance},
}

@inproceedings{isscc02,
  author = {Rosewater, Dan and Goldstein, Seth Copen},
  title = {Digital Logic Using Molecular Electronics},
  booktitle = {IEEE International Solid-State Circuits Conference
     (ISSCC)},
  year = {2002},
  month = {Feb},
  address = {San Francisco, CA},
  keywords = {Electronic Nanotechnology,Molecular
     Electronics,Two-Terminal Devices},
  url = {http://www.cs.cmu.edu/~seth/papers/isscc02.pdf},
}

@inproceedings{micro02,
  title = {From Molecules to Computers},
  author = {Goldstein, Seth Copen},
  year = {2002},
  address = {Istanbul, Turkey},
  booktitle = {Tutorial at 35th Annual International Symposium on
     Microarchitecture (Micro 35)},
  note = {Invited Tutorial},
  url = {http://www.cs.cmu.edu/~seth/papers/micro02.pdf},
  month = {Nov},
  keywords = {Electronic Nanotechnology},
}

@inproceedings{butts-iccad02,
  title = {Molecular electronics: devices, systems and tools for
     gigagate,gigabit chips},
  url = {http://www.cs.cmu.edu/~seth/papers/butts-iccad02.pdf},
  doi = {http://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167569},
  booktitle = {International Conference on Computer-Aided Design (
     ICCAD '02)},
  author = {Butts, Michael and DeHon, Andre and Goldstein, Seth
     Copen},
  abstract = {New electronics technologies are emerging which may
     carry us beyond the limits of lithographic processing down to
     molecular-scale feature sizes. Devices and interconnects can be
     made from a variety of molecules and materials including bistable
     and switchable organic molecules, carbon nanotubes, and,
     single-crystal semiconductor nanowires. They can be
     self-assembled into organized structures and attached onto
     lithographic substrates. This tutorial reviews emerging
     molecular-scale electronics technology for CAD and system
     designers and highlights where ICCAD research can help support
     this technology.},
  address = {San Jose, CA},
  year = {2002},
  pages = {433-440},
  note = {invited tutorial at},
  month = {Nov},
  keywords = {Electronic Nanotechnology,Reconfigurable
     Computing,molecular electronics},
}

@techreport{rg01,
  author = {Rosewater, Daniel L. and Goldstein, Seth Copen},
  title = {What makes a good molecular computing device?},
  institution = {Carnegie Mellon University},
  year = {2002},
  number = {CMU-CS-02-181},
  month = {Sep},
  keywords = {Electronic Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/rg01.pdf},
}

@inproceedings{goldstein-wvlsi01,
  title = {Electronic Nanotechnology and Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-wvlsi01.pdf},
  booktitle = {Proceedings of the IEEE Computer Society Workshop VLSI
     2001},
  author = {Goldstein, Seth Copen},
  year = {2001},
  pages = {10},
  month = {Apr},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Reconfigurable Computing},
}

@inproceedings{goldstein-foresight01,
  author = {Goldstein, Seth Copen and Ellenbogen, James and Almassiam,
     David and Brown, Matt and Cannarsa, Mark and Klein, Jesse and
     Schell, Schuyler and Washburn, Geoff and Ziegler, Matthew M},
  title = {MolSpice: Designing Molecular Logic Circuits},
  booktitle = {Ninth Foresight Conference on Molecular
     Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-foresight01.pdf},
  year = {2001},
  month = {Nov},
  address = {Santa Clara, CA},
  keywords = {Electronic Nanotechnology, Molecular Electronics, CAD},
}

@inproceedings{goldstein-isca01,
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  title = {{NanoFabrics}: Spatial Computing Using Molecular
     Electronics},
  booktitle = {Proceedings of the 28th International Symposium on
     Computer Architecture (ISCA)},
  month = {Jul},
  address = {{G\"{o}teborg, Sweden}},
  year = {2001},
  pages = {178--189},
  abstract = {The continuation of the remarkable exponential increases
     in processing power over the recent past faces imminent
     challenges due in part to the physics of deep-submicron CMOS
     devices and the costs of both chip masks and future fabrication
     plants. A promising solution to these problems is offered by an
     alternative to CMOS-based computing, chemically assembled
     electronic nanotechnology (CAEN). In this paper we outline how
     CAEN based computing can become a reality. We briefly describe
     recent work in CAEN and how CAEN will affect computer
     architecture. We show how the inherently reconfigurable natures
     of CAEN devices can be exploited to provide high-density chips
     with defect tolerance which will significantly reduce the cost of
     manufacturing. After developing the basic building blocks of a
     CAEN based computing devices we present some preliminary results
     which indicate that CAEN based computing devices can meet or
     exceed the performance of CMOS based devices.},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca01.pdf},
  keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
     Electronic Nanotechnology},
}

@inproceedings{goldstein-asplos00,
  title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
  booktitle = {The 10th International Conference on Architectural
     Support for Programming Languages and Operating Systems. (ASPLOS
     'IX)},
  author = {Goldstein, Seth Copen},
  address = {Cambridge, MA},
  year = {2000},
  month = {Nov},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Molecular Electronics,Reconfigurable Computing},
}