|
IEEE Transactions on Nanotechnology
Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln
volume 4, pages 215–228
Mar 1990
AbstractTechnologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations.
download pdf
@article{lincoln-tnano05,
title = {Nonphotolithographic Nanoscale Memory Density Prospects},
abstract = {Technologies are now emerging to construct
molecular-scale electronic wires and switches using bottom-up
self-assembly. This opens the possibility of constructing
nanoscale circuits and memories where active devices are just a
few nanometers square and wire pitches may be on the order of ten
nanometers. The features can be defined at this scale without
using photolithography. The available assembly techniques have
relatively high defect rates compared to conventional
lithographic integrated circuits and can only produce very
regular structures. Nonetheless, with proper memory organization,
it is reasonable to expect these technologies to provide memory
densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
power requirements under 0.6 W/Tb/s for random read operations.},
url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
journal = {IEEE Transactions on Nanotechnology},
author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
and Lincoln, Patrick},
year = {2005},
month = {Mar},
volume = {4},
issue = {2},
pages = {215-228},
keywords = {Fault and Defect Tolerance, electronic nanotechnology,
memory density, memory organization, molecular electronics},
doi = {10.1109/TNANO.2004.837849},
}
Related Papers
Memory Organization |
|
Nonphotolithographic Nanoscale Memory Density Prospects | pdf bib | |
Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln.
IEEE Transactions on Nanotechnology,
volume 4, pages 215–228, Mar 1990.
|
| @article{lincoln-tnano05,
title = {Nonphotolithographic Nanoscale Memory Density Prospects},
abstract = {Technologies are now emerging to construct
molecular-scale electronic wires and switches using bottom-up
self-assembly. This opens the possibility of constructing
nanoscale circuits and memories where active devices are just a
few nanometers square and wire pitches may be on the order of ten
nanometers. The features can be defined at this scale without
using photolithography. The available assembly techniques have
relatively high defect rates compared to conventional
lithographic integrated circuits and can only produce very
regular structures. Nonetheless, with proper memory organization,
it is reasonable to expect these technologies to provide memory
densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
power requirements under 0.6 W/Tb/s for random read operations.},
url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
journal = {IEEE Transactions on Nanotechnology},
author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
and Lincoln, Patrick},
year = {2005},
month = {Mar},
volume = {4},
issue = {2},
pages = {215-228},
keywords = {Fault and Defect Tolerance, electronic nanotechnology,
memory density, memory organization, molecular electronics},
doi = {10.1109/TNANO.2004.837849},
}
|
Electronic Nanotechnology |
|
Nonphotolithographic Nanoscale Memory Density Prospects | pdf bib | |
Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln.
IEEE Transactions on Nanotechnology,
volume 4, pages 215–228, Mar 1990.
|
| @article{lincoln-tnano05,
title = {Nonphotolithographic Nanoscale Memory Density Prospects},
abstract = {Technologies are now emerging to construct
molecular-scale electronic wires and switches using bottom-up
self-assembly. This opens the possibility of constructing
nanoscale circuits and memories where active devices are just a
few nanometers square and wire pitches may be on the order of ten
nanometers. The features can be defined at this scale without
using photolithography. The available assembly techniques have
relatively high defect rates compared to conventional
lithographic integrated circuits and can only produce very
regular structures. Nonetheless, with proper memory organization,
it is reasonable to expect these technologies to provide memory
densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
power requirements under 0.6 W/Tb/s for random read operations.},
url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
journal = {IEEE Transactions on Nanotechnology},
author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
and Lincoln, Patrick},
year = {2005},
month = {Mar},
volume = {4},
issue = {2},
pages = {215-228},
keywords = {Fault and Defect Tolerance, electronic nanotechnology,
memory density, memory organization, molecular electronics},
doi = {10.1109/TNANO.2004.837849},
}
|
|
The impact of the nanoscale on computing systems | pdf bib | |
Seth Copen Goldstein.
In IEEE/ACM International Conference on Computer-Aided Design, 2005 (ICCAD 2005),
pages 655–661, Nov 1990.
|
| @inproceedings{goldstein-iccad05,
title = {The impact of the nanoscale on computing systems},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-iccad05.pdf},
booktitle = {IEEE/ACM International Conference on Computer-Aided
Design, 2005 (ICCAD 2005)},
author = {Goldstein, Seth Copen},
year = {2005},
pages = {655-661},
address = {San Jose, CA},
month = {Nov},
keywords = {Electronic Nanotechnology,molecular electronics},
}
|
|
Why area might reduce power in nanoscale CMOS | pdf bib | |
Paul Beckett and Seth Copen Goldstein.
In IEEE International Symposium on Circuits and Systems, 2005, (ISCAS 2005),
volume 3, pages 2329–2332, May 1990.
|
| @inproceedings{beckett-iscas05,
title = {Why area might reduce power in nanoscale CMOS},
url = {http://www.cs.cmu.edu/~seth/papers/beckett-iscas05.pdf},
booktitle = {IEEE International Symposium on Circuits and Systems,
2005, (ISCAS 2005)},
author = {Beckett, Paul and Goldstein, Seth Copen},
year = {2005},
pages = {2329-2332},
volume = {3},
month = {May},
address = {Kobe, Japan},
abstract = {In this paper we explore the relationship between power
and area. By exploiting parallelism (and thus using more area)
one can reduce the switching frequency allowing a reduction in
VDD which results in a reduction in power. Under a scaling regime
which allows threshold voltage to increase as VDD decreases we
find that dynamic and subthreshold power loss in CMOS exhibit a
dependence on area proportional to A^((\sigma^-3)/\sigma) while
gate leakage power proportional to A^((\sigma^-6)/\sigma) and
short circuit power A^((\sigma^-6)/\sigma). Thus, with the large
number of devices at our disposal we can exploit techniques such
as spatial computing--tailoring the program directly to the
hardware--to overcome the negative effects of scaling. The value
of s describes the effectiveness of the technique for a
particular circuit and/or algorithm--for circuits that exhibit a
value of \sigma <= 3, power will be a constant or reducing
function of area. We briefly speculate on how \sigma might be
influenced by a move to nanoscale technology.},
keywords = {Electronic Nanotechnology,Power,Energy},
}
|
|
Computing Without Processors | bib | |
Seth Copen Goldstein.
In International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'04),
pages 29–32, Jun 1990.
|
| @inproceedings{goldstein04-ersa04,
author = {Goldstein, Seth Copen},
title = {Computing Without Processors},
booktitle = {International Conference on Engineering of
Reconfigurable Systems and Algorithms (ERSA'04)},
abstract = {The continuation of the remarkable exponential increases
in processing power over the recent past faces imminent
challenges due in part rising cost of design and manufacturing
and the physics of deep-submicron semiconductor devices. In this
talk we will discuss a promising alternative to ever more complex
processors, application specific hardware (ASH). The ASH model is
based on compiling high-level programs directly into circuits,
which can either be fabricated as ASICs or more reasonably
converted in configurations for reconfigurable devices. We will
discuss the challenges involved in compiling sequential
programming languages into circuits and the challenges in
implementing those circuits in a scalable and power efficient
manner.},
address = {Las Vegas, NV},
month = {Jun},
year = {2004},
pages = {29--32},
keywords = {Reconfigurable Computing, Electronic Nanotechnology,
Fault and Defect Tolerance},
}
|
|
Defect Tolerance at the End of the Roadmap | bib | |
Mahim Mishra and Seth Copen Goldstein.
In Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation,
1990.
|
| @incollection{mishra-nqmc04,
title = {Defect Tolerance at the End of the Roadmap},
booktitle = {Nano, Quantum and Molecular Computing: Implications to
High Level Design and Validation},
author = {Mishra, Mahim and Goldstein, Seth Copen},
year = {2004},
editor = {Sandeep K. Shukla and R. Iris Bahar},
publisher = {Kluwer Academic Publishers},
isbn = {1-4020-80670},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing,Phoenix,molecular
electronics},
}
|
|
The Challenges and Opportunities of Nanoelectronics | pdf bib | |
Seth Copen Goldstein.
In Proceedings of Government Microcircuit Applications and Critical Technology Conference (GOMAC Tech 04),
Mar 1990.
|
| @inproceedings{goldstein-gomac04,
title = {The Challenges and Opportunities of Nanoelectronics},
author = {Goldstein, Seth Copen},
booktitle = {Proceedings of Government Microcircuit Applications and
Critical Technology Conference (GOMAC Tech 04)},
year = {2004},
address = {Monterey, CA},
keywords = {Electronic Nanotechnology},
month = {Mar},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-gomac04.pdf},
}
|
|
Translating ANSI C to Asynchronous Circuits | pdf bib | |
Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein.
In 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '04),
Apr 1990.
|
| @inproceedings{budiu-async04,
title = {Translating ANSI C to Asynchronous Circuits},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
booktitle = {10th IEEE International Symposium on Asynchronous
Circuits and Systems (ASYNC '04)},
author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
Tiberiu and Goldstein, Seth Copen},
address = {Crete, Greece},
year = {2004},
month = {Apr},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
Computing},
}
|
|
Models and Abstractions for Nanoelectronics | bib | |
Seth Copen Goldstein and Y Zhu.
In Third IEEE Conference on Nanotechnology (IEEE-NANO 2003),
Aug 1990.
|
| @inproceedings{goldstein-inano03,
title = {Models and Abstractions for Nanoelectronics},
booktitle = {Third IEEE Conference on Nanotechnology (IEEE-NANO
2003)},
author = {Goldstein, Seth Copen and Zhu, Y},
address = {San Francisco, CA},
year = {2003},
month = {Aug},
keywords = {Electronic Nanotechnology},
}
|
|
Molecular Electronics: From Devices and Interconnect to Circuits and Architecture | pdf bib | |
Mircea R Stan, Paul D Franzon, Seth Copen Goldstein, John C Lach, and Matthew M Ziegler.
Proceedings of the IEEE,
91(11), Nov 1990.
|
| @article{mircea-ieee03,
title = {Molecular Electronics: From Devices and Interconnect to
Circuits and Architecture},
author = {Stan, Mircea R and Franzon, Paul D and Goldstein, Seth
Copen and Lach, John C and Ziegler, Matthew M},
journal = {Proceedings of the IEEE},
year = {2003},
volume = {91},
number = {11},
month = {Nov},
keywords = {Electronic Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/mircea-ieee03.pdf},
}
|
|
Molecules, Gates, Circuits, Computer | pdf bib | |
Seth Copen Goldstein and Mihai Budiu.
In Molecular Nanoelectronics,
Jan 1990.
|
| @incollection{goldstein-mn03,
title = {Molecules, Gates, Circuits, Computer},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
booktitle = {Molecular Nanoelectronics},
author = {Goldstein, Seth Copen and Budiu, Mihai},
year = {2003},
editor = {Mark A. Reed and Takhee Lee},
publisher = {American Scientific Publishers},
address = {Stevenson Ranch, CA},
month = {Jan},
isbn = {1-588883-006-3},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Reconfigurable Computing,Spatial
Computing,electronic nanotechnology,molecular electronics},
}
|
|
Nano, Quantum, and Molecular Computing: Are We Ready for the Validation and Test Challenges | pdf bib talk | |
Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forest Brewer, Kaustav Banerjee, and Sankar Basu.
In Eighth IEEE International High-Level Design Validation and Test Workshop,
pages 307, Nov 1990.
|
| @inproceedings{shukla-hldvt03,
title = {Nano, Quantum, and Molecular Computing: Are We Ready for
the Validation and Test Challenges},
url = {http://www.cs.cmu.edu/~seth/papers/shukla-hldvt03.pdf},
talk = {http://www.cs.cmu.edu/~seth/hldvt03-goldstein.pdf},
booktitle = {Eighth IEEE International High-Level Design Validation
and Test Workshop},
author = {Shukla, Sandeep K. and Karri, Ramesh and Goldstein, Seth
Copen and Brewer, Forest and Banerjee, Kaustav and Basu, Sankar},
year = {2003},
month = {Nov},
pages = {307},
address = {San Francisco, CA},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,molecular electronics},
}
|
|
Reconfigurable Computing and Electronic Nanotechnology | pdf bib | |
Seth Copen Goldstein, Mihai Budiu, Mahim Mishra, and Girish Venkataramani.
In Proceedings of the IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2003),
pages 132–143, Jun 1990.
|
| @inproceedings{goldstein-asap03,
title = {Reconfigurable Computing and Electronic Nanotechnology},
author = {Goldstein, Seth Copen and Budiu, Mihai and Mishra, Mahim
and Venkataramani, Girish},
booktitle = {Proceedings of the {IEEE} 14th International Conference
on Application-specific Systems, Architectures and Processors
({ASAP} 2003)},
year = {2003},
address = {The Hague, Netherlands},
month = {Jun},
note = {Invited paper},
pages = {132-143},
abstract = {In this paper we examine the opportunities brought about
by recent progress in electronic nanotechnology and describe the
methods needed to harness them for building a new computer
architecture. In this process we decompose some traditional
abstractions, such as the transistor, into fine-grain pieces,
such as signal restoration and input-output isolation. We also
show how we can forgo the extreme reliability of CMOS circuits
for low-cost chemical self-assembly at the expense of large
manufacturing defect densities. We discuss advanced testing
methods which can be used to recover perfect functionality from
unreliable parts. We proceed to show how the molecular switch,
the regularity of the circuits created by self-assembly and the
high defect densities logically require the use of reconfigurable
hardware as a basic building block for hardware design. We then
capitalize on the convergence of compilation and hardware
synthesis (which takes place when programming reconfigurable
hardware) to propose the complete elimination of the
instruction-set architecture from the system architecture, and
the synthesis of asynchronous dataflow machines directly from
high-level programming languages, such as C. We discuss in some
detail a scalable compilation system that perform this task.},
keywords = {Reconfigurable Computing, Electronic Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asap03.pdf},
}
|
|
Reconfigurable Nanoelectronics and Defect Tolerance | bib | |
Seth Copen Goldstein.
In Proceedings of High-level design, verification, and test,
1990.
|
| @inproceedings{goldstein-hldvt03,
title = {Reconfigurable Nanoelectronics and Defect Tolerance},
author = {Goldstein, Seth Copen},
booktitle = {Proceedings of High-level design, verification, and
test},
year = {2003},
keywords = {Reconfigurable Computing, Electronic Nanotechnology,
Fault and Defect Tolerance},
}
|
|
Digital Logic Using Molecular Electronics | pdf bib | |
Dan Rosewater and Seth Copen Goldstein.
In IEEE International Solid-State Circuits Conference (ISSCC),
Feb 1990.
|
| @inproceedings{isscc02,
author = {Rosewater, Dan and Goldstein, Seth Copen},
title = {Digital Logic Using Molecular Electronics},
booktitle = {IEEE International Solid-State Circuits Conference
(ISSCC)},
year = {2002},
month = {Feb},
address = {San Francisco, CA},
keywords = {Electronic Nanotechnology,Molecular
Electronics,Two-Terminal Devices},
url = {http://www.cs.cmu.edu/~seth/papers/isscc02.pdf},
}
|
|
From Molecules to Computers | pdf bib | |
Seth Copen Goldstein.
In Tutorial at 35th Annual International Symposium on Microarchitecture (Micro 35),
Nov 1990.
|
| @inproceedings{micro02,
title = {From Molecules to Computers},
author = {Goldstein, Seth Copen},
year = {2002},
address = {Istanbul, Turkey},
booktitle = {Tutorial at 35th Annual International Symposium on
Microarchitecture (Micro 35)},
note = {Invited Tutorial},
url = {http://www.cs.cmu.edu/~seth/papers/micro02.pdf},
month = {Nov},
keywords = {Electronic Nanotechnology},
}
|
|
Molecular electronics: devices, systems and tools for gigagate,gigabit chips | pdf bib | |
Michael Butts, Andre DeHon, and Seth Copen Goldstein.
In International Conference on Computer-Aided Design ( ICCAD '02),
pages 433–440, Nov 1990.
|
| @inproceedings{butts-iccad02,
title = {Molecular electronics: devices, systems and tools for
gigagate,gigabit chips},
url = {http://www.cs.cmu.edu/~seth/papers/butts-iccad02.pdf},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167569},
booktitle = {International Conference on Computer-Aided Design (
ICCAD '02)},
author = {Butts, Michael and DeHon, Andre and Goldstein, Seth
Copen},
abstract = {New electronics technologies are emerging which may
carry us beyond the limits of lithographic processing down to
molecular-scale feature sizes. Devices and interconnects can be
made from a variety of molecules and materials including bistable
and switchable organic molecules, carbon nanotubes, and,
single-crystal semiconductor nanowires. They can be
self-assembled into organized structures and attached onto
lithographic substrates. This tutorial reviews emerging
molecular-scale electronics technology for CAD and system
designers and highlights where ICCAD research can help support
this technology.},
address = {San Jose, CA},
year = {2002},
pages = {433-440},
note = {invited tutorial at},
month = {Nov},
keywords = {Electronic Nanotechnology,Reconfigurable
Computing,molecular electronics},
}
|
|
What makes a good molecular computing device? | pdf bib | |
Daniel L. Rosewater and Seth Copen Goldstein.
Carnegie Mellon University Technical Report No. CMU-CS-02-181,
Sep 1990.
|
| @techreport{rg01,
author = {Rosewater, Daniel L. and Goldstein, Seth Copen},
title = {What makes a good molecular computing device?},
institution = {Carnegie Mellon University},
year = {2002},
number = {CMU-CS-02-181},
month = {Sep},
keywords = {Electronic Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/rg01.pdf},
}
|
|
Electronic Nanotechnology and Reconfigurable Computing | pdf bib | |
Seth Copen Goldstein.
In Proceedings of the IEEE Computer Society Workshop VLSI 2001,
pages 10, Apr 1990.
|
| @inproceedings{goldstein-wvlsi01,
title = {Electronic Nanotechnology and Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-wvlsi01.pdf},
booktitle = {Proceedings of the IEEE Computer Society Workshop VLSI
2001},
author = {Goldstein, Seth Copen},
year = {2001},
pages = {10},
month = {Apr},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing},
}
|
|
MolSpice: Designing Molecular Logic Circuits | pdf bib | |
Seth Copen Goldstein, James Ellenbogen, David Almassiam, Matt Brown, Mark Cannarsa, Jesse Klein, Schuyler Schell, Geoff Washburn, and Matthew M Ziegler.
In Ninth Foresight Conference on Molecular Nanotechnology,
Nov 1990.
|
| @inproceedings{goldstein-foresight01,
author = {Goldstein, Seth Copen and Ellenbogen, James and Almassiam,
David and Brown, Matt and Cannarsa, Mark and Klein, Jesse and
Schell, Schuyler and Washburn, Geoff and Ziegler, Matthew M},
title = {MolSpice: Designing Molecular Logic Circuits},
booktitle = {Ninth Foresight Conference on Molecular
Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-foresight01.pdf},
year = {2001},
month = {Nov},
address = {Santa Clara, CA},
keywords = {Electronic Nanotechnology, Molecular Electronics, CAD},
}
|
|
NanoFabrics: Spatial Computing Using Molecular Electronics | pdf bib | |
Seth Copen Goldstein and Mihai Budiu.
In Proceedings of the 28th International Symposium on Computer Architecture (ISCA),
pages 178–189, Jul 1990.
|
| @inproceedings{goldstein-isca01,
author = {Goldstein, Seth Copen and Budiu, Mihai},
title = {{NanoFabrics}: Spatial Computing Using Molecular
Electronics},
booktitle = {Proceedings of the 28th International Symposium on
Computer Architecture (ISCA)},
month = {Jul},
address = {{G\"{o}teborg, Sweden}},
year = {2001},
pages = {178--189},
abstract = {The continuation of the remarkable exponential increases
in processing power over the recent past faces imminent
challenges due in part to the physics of deep-submicron CMOS
devices and the costs of both chip masks and future fabrication
plants. A promising solution to these problems is offered by an
alternative to CMOS-based computing, chemically assembled
electronic nanotechnology (CAEN). In this paper we outline how
CAEN based computing can become a reality. We briefly describe
recent work in CAEN and how CAEN will affect computer
architecture. We show how the inherently reconfigurable natures
of CAEN devices can be exploited to provide high-density chips
with defect tolerance which will significantly reduce the cost of
manufacturing. After developing the basic building blocks of a
CAEN based computing devices we present some preliminary results
which indicate that CAEN based computing devices can meet or
exceed the performance of CMOS based devices.},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca01.pdf},
keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
Electronic Nanotechnology},
}
|
|
NanoFabrics: Extending Moore's Law Beyond the CMOS Era | pdf bib | |
Seth Copen Goldstein.
In The 10th International Conference on Architectural Support for Programming Languages and Operating Systems. (ASPLOS 'IX),
Nov 1990.
|
| @inproceedings{goldstein-asplos00,
title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
booktitle = {The 10th International Conference on Architectural
Support for Programming Languages and Operating Systems. (ASPLOS
'IX)},
author = {Goldstein, Seth Copen},
address = {Cambridge, MA},
year = {2000},
month = {Nov},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Molecular Electronics,Reconfigurable Computing},
}
|
Fault And Defect Tolerance |
|
Nonphotolithographic Nanoscale Memory Density Prospects | pdf bib | |
Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln.
IEEE Transactions on Nanotechnology,
volume 4, pages 215–228, Mar 1990.
|
| @article{lincoln-tnano05,
title = {Nonphotolithographic Nanoscale Memory Density Prospects},
abstract = {Technologies are now emerging to construct
molecular-scale electronic wires and switches using bottom-up
self-assembly. This opens the possibility of constructing
nanoscale circuits and memories where active devices are just a
few nanometers square and wire pitches may be on the order of ten
nanometers. The features can be defined at this scale without
using photolithography. The available assembly techniques have
relatively high defect rates compared to conventional
lithographic integrated circuits and can only produce very
regular structures. Nonetheless, with proper memory organization,
it is reasonable to expect these technologies to provide memory
densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
power requirements under 0.6 W/Tb/s for random read operations.},
url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
journal = {IEEE Transactions on Nanotechnology},
author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
and Lincoln, Patrick},
year = {2005},
month = {Mar},
volume = {4},
issue = {2},
pages = {215-228},
keywords = {Fault and Defect Tolerance, electronic nanotechnology,
memory density, memory organization, molecular electronics},
doi = {10.1109/TNANO.2004.837849},
}
|
|
Computing Without Processors | bib | |
Seth Copen Goldstein.
In International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'04),
pages 29–32, Jun 1990.
|
| @inproceedings{goldstein04-ersa04,
author = {Goldstein, Seth Copen},
title = {Computing Without Processors},
booktitle = {International Conference on Engineering of
Reconfigurable Systems and Algorithms (ERSA'04)},
abstract = {The continuation of the remarkable exponential increases
in processing power over the recent past faces imminent
challenges due in part rising cost of design and manufacturing
and the physics of deep-submicron semiconductor devices. In this
talk we will discuss a promising alternative to ever more complex
processors, application specific hardware (ASH). The ASH model is
based on compiling high-level programs directly into circuits,
which can either be fabricated as ASICs or more reasonably
converted in configurations for reconfigurable devices. We will
discuss the challenges involved in compiling sequential
programming languages into circuits and the challenges in
implementing those circuits in a scalable and power efficient
manner.},
address = {Las Vegas, NV},
month = {Jun},
year = {2004},
pages = {29--32},
keywords = {Reconfigurable Computing, Electronic Nanotechnology,
Fault and Defect Tolerance},
}
|
|
Defect Tolerance at the End of the Roadmap | bib | |
Mahim Mishra and Seth Copen Goldstein.
In Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation,
1990.
|
| @incollection{mishra-nqmc04,
title = {Defect Tolerance at the End of the Roadmap},
booktitle = {Nano, Quantum and Molecular Computing: Implications to
High Level Design and Validation},
author = {Mishra, Mahim and Goldstein, Seth Copen},
year = {2004},
editor = {Sandeep K. Shukla and R. Iris Bahar},
publisher = {Kluwer Academic Publishers},
isbn = {1-4020-80670},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing,Phoenix,molecular
electronics},
}
|
|
Translating ANSI C to Asynchronous Circuits | pdf bib | |
Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein.
In 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '04),
Apr 1990.
|
| @inproceedings{budiu-async04,
title = {Translating ANSI C to Asynchronous Circuits},
url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
booktitle = {10th IEEE International Symposium on Asynchronous
Circuits and Systems (ASYNC '04)},
author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
Tiberiu and Goldstein, Seth Copen},
address = {Crete, Greece},
year = {2004},
month = {Apr},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
Computing},
}
|
|
Defect Tolerance After the Roadmap | pdf bib | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the 10th International Test Synthesis Workshop (ITSW),
Mar 1990.
|
| @inproceedings{mishra-itsw03,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Defect Tolerance After the Roadmap},
booktitle = {Proceedings of the 10th International Test Synthesis
Workshop (ITSW)},
month = {Mar},
year = {2003},
address = {Santa Barbara, {CA}},
keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
Fault and Defect Tolerance},
url = {http://www.cs.cmu.edu/~seth/papers/mishra-itsw03.pdf},
}
|
|
Defect Tolerance at the End of the Roadmap | pdf bib | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the International Test Conference (ITC), 2003,
Sep 1990.
|
| @inproceedings{mishra-itc03,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Defect Tolerance at the End of the Roadmap},
booktitle = {Proceedings of the International Test Conference
({ITC}), 2003},
month = {Sep},
year = {2003},
address = {Charlotte, {NC}},
url = {http://www.cs.cmu.edu/~seth/papers/mishra-itc03.pdf},
abstract = {Defect tolerance will become more important as feature
sizes shrink closer to single digit nanometer dimensions. This is
true whether the chips are manufactured using top-down methods
(e.g., photolithography) or bottom-up methods (e.g., chemically
assembled electronic nanotechnology, or CAEN). In this paper, we
propose a defect tolerance methodology centered around
reconfigurable devices, a scalable testing method, and dynamic
place-and-route. Our methodology is particularly well suited for
CAEN.},
keywords = {Spatial Computing, Reconfigurable
Computing,Phoenix,Fault and Defect Tolerance},
}
|
|
Molecules, Gates, Circuits, Computer | pdf bib | |
Seth Copen Goldstein and Mihai Budiu.
In Molecular Nanoelectronics,
Jan 1990.
|
| @incollection{goldstein-mn03,
title = {Molecules, Gates, Circuits, Computer},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
booktitle = {Molecular Nanoelectronics},
author = {Goldstein, Seth Copen and Budiu, Mihai},
year = {2003},
editor = {Mark A. Reed and Takhee Lee},
publisher = {American Scientific Publishers},
address = {Stevenson Ranch, CA},
month = {Jan},
isbn = {1-588883-006-3},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Reconfigurable Computing,Spatial
Computing,electronic nanotechnology,molecular electronics},
}
|
|
Nano, Quantum, and Molecular Computing: Are We Ready for the Validation and Test Challenges | pdf bib talk | |
Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forest Brewer, Kaustav Banerjee, and Sankar Basu.
In Eighth IEEE International High-Level Design Validation and Test Workshop,
pages 307, Nov 1990.
|
| @inproceedings{shukla-hldvt03,
title = {Nano, Quantum, and Molecular Computing: Are We Ready for
the Validation and Test Challenges},
url = {http://www.cs.cmu.edu/~seth/papers/shukla-hldvt03.pdf},
talk = {http://www.cs.cmu.edu/~seth/hldvt03-goldstein.pdf},
booktitle = {Eighth IEEE International High-Level Design Validation
and Test Workshop},
author = {Shukla, Sandeep K. and Karri, Ramesh and Goldstein, Seth
Copen and Brewer, Forest and Banerjee, Kaustav and Basu, Sankar},
year = {2003},
month = {Nov},
pages = {307},
address = {San Francisco, CA},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,molecular electronics},
}
|
|
Reconfigurable Nanoelectronics and Defect Tolerance | bib | |
Seth Copen Goldstein.
In Proceedings of High-level design, verification, and test,
1990.
|
| @inproceedings{goldstein-hldvt03,
title = {Reconfigurable Nanoelectronics and Defect Tolerance},
author = {Goldstein, Seth Copen},
booktitle = {Proceedings of High-level design, verification, and
test},
year = {2003},
keywords = {Reconfigurable Computing, Electronic Nanotechnology,
Fault and Defect Tolerance},
}
|
|
Scalable Defect Tolerance for Molecular Electronics | pdf bib | |
Mahim Mishra and Seth Copen Goldstein.
In Proceedings of the 1st Workshop on Non-Silicon Computing (NSC-1),
1990.
|
| @inproceedings{mishra_goldstein_nsc1,
author = {Mishra, Mahim and Goldstein, Seth Copen},
title = {Scalable Defect Tolerance for Molecular Electronics},
booktitle = {Proceedings of the 1st Workshop on Non-Silicon
Computing (NSC-1)},
address = {{Cambridge, MA}},
year = {2002},
url = {http://www.cs.cmu.edu/~seth/papers/mishra_goldstein_nsc1.pdf},
abstract = {Chemically assembled electronic nanotechnology (CAEN) is
a promising alternative to CMOS-based computing. However,
CAEN-based circuits are expected to have huge defect densities.
To solve this problem CAEN can be used to build reconfigurable
fabrics which, assuming the defects can be found, are inherently
defect tolerant. In this paper, we propose a scalable testing
methodology for finding defects in reconfigurable devices.},
keywords = {Reconfigurable Computing, Phoenix,Fault and Defect
Tolerance},
}
|
|
Electronic Nanotechnology and Reconfigurable Computing | pdf bib | |
Seth Copen Goldstein.
In Proceedings of the IEEE Computer Society Workshop VLSI 2001,
pages 10, Apr 1990.
|
| @inproceedings{goldstein-wvlsi01,
title = {Electronic Nanotechnology and Reconfigurable Computing},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-wvlsi01.pdf},
booktitle = {Proceedings of the IEEE Computer Society Workshop VLSI
2001},
author = {Goldstein, Seth Copen},
year = {2001},
pages = {10},
month = {Apr},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing},
}
|
|
Fault Tolerance in Run-time Reconfigurable Architectures | bib | |
Peter M. Kamarchik, Steven Sinha, and Seth Copen Goldstein.
In IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '00),
Apr 1990.
|
| @inproceedings{KSS00,
author = {Kamarchik, Peter M. and Sinha, Steven and Goldstein, Seth
Copen},
title = {Fault Tolerance in Run-time Reconfigurable Architectures},
booktitle = {IEEE Symposium on FPGAs for Custom Computing Machines
(FCCM '00)},
year = {2000},
month = {Apr},
address = {Napa, CA},
keywords = {PipeRench, Fault and Defect Tolerance},
}
|
|
NanoFabrics: Extending Moore's Law Beyond the CMOS Era | pdf bib | |
Seth Copen Goldstein.
In The 10th International Conference on Architectural Support for Programming Languages and Operating Systems. (ASPLOS 'IX),
Nov 1990.
|
| @inproceedings{goldstein-asplos00,
title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
booktitle = {The 10th International Conference on Architectural
Support for Programming Languages and Operating Systems. (ASPLOS
'IX)},
author = {Goldstein, Seth Copen},
address = {Cambridge, MA},
year = {2000},
month = {Nov},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Molecular Electronics,Reconfigurable Computing},
}
|
|
Tunable Fault Tolerance for Runtime Reconfigurable Architectures | pdf bib | |
Steven K. Sinha, Peter M. Kamarchik, and Seth Copen Goldstein.
In 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000),
pages 185–192, Apr 1990.
|
| @inproceedings{sinha-fccm00,
title = {Tunable Fault Tolerance for Runtime Reconfigurable
Architectures},
url = {http://www.cs.cmu.edu/~seth/papers/sinha-fccm00.pdf},
booktitle = {8th IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM 2000)},
author = {Sinha, Steven K. and Kamarchik, Peter M. and Goldstein,
Seth Copen},
abstract = {Fault tolerance is becoming an increasingly important
issue, especially in mission-critical applications where data
integrity is a paramount concern. Performance, however, remains a
large driving force in the market place. Runtime reconfigurable
hardware architectures have the power to balance fault tolerance
with performance, allowing the amount of fault tolerance to be
tuned at run-time. This paper describes a new built-in self-test
designed to run on, and take advantage of, runtime reconfigurable
architectures using the PipeRench architecture as a model. In
addition, this paper introduces a new metric by which a user can
set the desired fault tolerance of a runtime reconfigurable
device},
doi = {10.1109/FPGA.2000.903405},
year = {2000},
pages = {185-192},
isbn = {0-7695-0871-5},
address = {Napa Valley, CA},
month = {Apr},
keywords = {Fault And Defect Tolerance,PipeRench,Reconfigurable
Computing},
}
|
|
Tunable Fault Tolernace via Test and Reconfiguration | pdf bib | |
Shawn Blanton, Seth Copen Goldstein, and Herman Schmit.
In Digest of FastAbstracts of the 28th Annual International Symposium on Fault-Tolerant Computing,
pages 9–10, Jun 1990.
|
| @inproceedings{blanton-ftc98,
author = {Blanton, Shawn and Goldstein, Seth Copen and Schmit,
Herman},
title = {Tunable Fault Tolernace via Test and Reconfiguration},
booktitle = {Digest of FastAbstracts of the 28th Annual
International Symposium on Fault-Tolerant Computing},
year = {1998},
month = {Jun},
pages = {9--10},
keywords = {PipeRench, Fault and Defect Tolerance},
url = {http://www.cs.cmu.edu/~seth/papers/blanton-ftc98.pdf},
}
|
Molecular Electronics |
|
Nonphotolithographic Nanoscale Memory Density Prospects | pdf bib | |
Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln.
IEEE Transactions on Nanotechnology,
volume 4, pages 215–228, Mar 1990.
|
| @article{lincoln-tnano05,
title = {Nonphotolithographic Nanoscale Memory Density Prospects},
abstract = {Technologies are now emerging to construct
molecular-scale electronic wires and switches using bottom-up
self-assembly. This opens the possibility of constructing
nanoscale circuits and memories where active devices are just a
few nanometers square and wire pitches may be on the order of ten
nanometers. The features can be defined at this scale without
using photolithography. The available assembly techniques have
relatively high defect rates compared to conventional
lithographic integrated circuits and can only produce very
regular structures. Nonetheless, with proper memory organization,
it is reasonable to expect these technologies to provide memory
densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
power requirements under 0.6 W/Tb/s for random read operations.},
url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
journal = {IEEE Transactions on Nanotechnology},
author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
and Lincoln, Patrick},
year = {2005},
month = {Mar},
volume = {4},
issue = {2},
pages = {215-228},
keywords = {Fault and Defect Tolerance, electronic nanotechnology,
memory density, memory organization, molecular electronics},
doi = {10.1109/TNANO.2004.837849},
}
|
|
The impact of the nanoscale on computing systems | pdf bib | |
Seth Copen Goldstein.
In IEEE/ACM International Conference on Computer-Aided Design, 2005 (ICCAD 2005),
pages 655–661, Nov 1990.
|
| @inproceedings{goldstein-iccad05,
title = {The impact of the nanoscale on computing systems},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-iccad05.pdf},
booktitle = {IEEE/ACM International Conference on Computer-Aided
Design, 2005 (ICCAD 2005)},
author = {Goldstein, Seth Copen},
year = {2005},
pages = {655-661},
address = {San Jose, CA},
month = {Nov},
keywords = {Electronic Nanotechnology,molecular electronics},
}
|
|
Defect Tolerance at the End of the Roadmap | bib | |
Mahim Mishra and Seth Copen Goldstein.
In Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation,
1990.
|
| @incollection{mishra-nqmc04,
title = {Defect Tolerance at the End of the Roadmap},
booktitle = {Nano, Quantum and Molecular Computing: Implications to
High Level Design and Validation},
author = {Mishra, Mahim and Goldstein, Seth Copen},
year = {2004},
editor = {Sandeep K. Shukla and R. Iris Bahar},
publisher = {Kluwer Academic Publishers},
isbn = {1-4020-80670},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Reconfigurable Computing,Phoenix,molecular
electronics},
}
|
|
Methods of chemically assembled electronic nanotechnology circuit fabrication | pdf bib | |
Seth Copen Goldstein and Daniel L. Rosewater.
United States Patent No. 7,064,000. Issued June 20, 2006,
Jul 1990.
|
| @misc{patent06,
author = {Goldstein, Seth Copen and Rosewater, Daniel L.},
title = {Methods of chemically assembled electronic nanotechnology
circuit fabrication},
howpublished = {United States Patent No. 7,064,000. Issued June 20,
2006},
month = {Jul},
year = {2004},
url = {http://www.cs.cmu.edu/~seth/papers/patent06.pdf},
keywords = {Molecular Electronics,Two-Terminal Devices},
abstract = {Chemically assembled electronic nanotechnology (CAEN)
provides an alternative to using Complementary Metal Oxide
Semiconductor (CMOS) for constructing circuits with feature sizes
in the tens of nanometers. A molecular latch and a method using
the latch that enables it to act as a state holding device,
perform voltage restoration, and to provide I/O isolation is
disclosed.},
url = {http://www.cs.cmu.edu/~seth/papers/patent06.pdf},
}
|
|
Molecules, Gates, Circuits, Computer | pdf bib | |
Seth Copen Goldstein and Mihai Budiu.
In Molecular Nanoelectronics,
Jan 1990.
|
| @incollection{goldstein-mn03,
title = {Molecules, Gates, Circuits, Computer},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
booktitle = {Molecular Nanoelectronics},
author = {Goldstein, Seth Copen and Budiu, Mihai},
year = {2003},
editor = {Mark A. Reed and Takhee Lee},
publisher = {American Scientific Publishers},
address = {Stevenson Ranch, CA},
month = {Jan},
isbn = {1-588883-006-3},
keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
and Defect Tolerance,Reconfigurable Computing,Spatial
Computing,electronic nanotechnology,molecular electronics},
}
|
|
Nano, Quantum, and Molecular Computing: Are We Ready for the Validation and Test Challenges | pdf bib talk | |
Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forest Brewer, Kaustav Banerjee, and Sankar Basu.
In Eighth IEEE International High-Level Design Validation and Test Workshop,
pages 307, Nov 1990.
|
| @inproceedings{shukla-hldvt03,
title = {Nano, Quantum, and Molecular Computing: Are We Ready for
the Validation and Test Challenges},
url = {http://www.cs.cmu.edu/~seth/papers/shukla-hldvt03.pdf},
talk = {http://www.cs.cmu.edu/~seth/hldvt03-goldstein.pdf},
booktitle = {Eighth IEEE International High-Level Design Validation
and Test Workshop},
author = {Shukla, Sandeep K. and Karri, Ramesh and Goldstein, Seth
Copen and Brewer, Forest and Banerjee, Kaustav and Basu, Sankar},
year = {2003},
month = {Nov},
pages = {307},
address = {San Francisco, CA},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,molecular electronics},
}
|
|
Digital Logic Using Molecular Electronics | pdf bib | |
Dan Rosewater and Seth Copen Goldstein.
In IEEE International Solid-State Circuits Conference (ISSCC),
Feb 1990.
|
| @inproceedings{isscc02,
author = {Rosewater, Dan and Goldstein, Seth Copen},
title = {Digital Logic Using Molecular Electronics},
booktitle = {IEEE International Solid-State Circuits Conference
(ISSCC)},
year = {2002},
month = {Feb},
address = {San Francisco, CA},
keywords = {Electronic Nanotechnology,Molecular
Electronics,Two-Terminal Devices},
url = {http://www.cs.cmu.edu/~seth/papers/isscc02.pdf},
}
|
|
Molecular electronics: devices, systems and tools for gigagate,gigabit chips | pdf bib | |
Michael Butts, Andre DeHon, and Seth Copen Goldstein.
In International Conference on Computer-Aided Design ( ICCAD '02),
pages 433–440, Nov 1990.
|
| @inproceedings{butts-iccad02,
title = {Molecular electronics: devices, systems and tools for
gigagate,gigabit chips},
url = {http://www.cs.cmu.edu/~seth/papers/butts-iccad02.pdf},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167569},
booktitle = {International Conference on Computer-Aided Design (
ICCAD '02)},
author = {Butts, Michael and DeHon, Andre and Goldstein, Seth
Copen},
abstract = {New electronics technologies are emerging which may
carry us beyond the limits of lithographic processing down to
molecular-scale feature sizes. Devices and interconnects can be
made from a variety of molecules and materials including bistable
and switchable organic molecules, carbon nanotubes, and,
single-crystal semiconductor nanowires. They can be
self-assembled into organized structures and attached onto
lithographic substrates. This tutorial reviews emerging
molecular-scale electronics technology for CAD and system
designers and highlights where ICCAD research can help support
this technology.},
address = {San Jose, CA},
year = {2002},
pages = {433-440},
note = {invited tutorial at},
month = {Nov},
keywords = {Electronic Nanotechnology,Reconfigurable
Computing,molecular electronics},
}
|
|
Molecular scale latch and associated clocking scheme to provide gain, memory and I/O isolation | pdf bib | |
Seth Copen Goldstein and Daniel L. Rosewater.
United States Patent No. 6,777,982. Issued August 17, 2004,
Apr 1990.
|
| @misc{patent04,
author = {Goldstein, Seth Copen and Rosewater, Daniel L.},
title = {Molecular scale latch and associated clocking scheme to
provide gain, memory and I/O isolation},
howpublished = {United States Patent No. 6,777,982. Issued August
17, 2004},
month = {Apr},
url = {http://www.cs.cmu.edu/~seth/papers/patent04.pdf},
year = {2002},
keywords = {Molecular Electronics,Two-Terminal Devices},
abstract = {Chemically assembled electronic nanotechnology (CAEN)
provides an alternative to using Complementary Metal Oxide
Semiconductor (CMOS) for constructing circuits with feature sizes
in the tens of nanometers. A molecular latch and a method using
the latch that enables it to act as a state holding device,
perform voltage restoration, and to provide I/O isolation is
disclosed.},
url = {http://www.cs.cmu.edu/~seth/papers/patent04.pdf},
}
|
|
MolSpice: Designing Molecular Logic Circuits | pdf bib | |
Seth Copen Goldstein, James Ellenbogen, David Almassiam, Matt Brown, Mark Cannarsa, Jesse Klein, Schuyler Schell, Geoff Washburn, and Matthew M Ziegler.
In Ninth Foresight Conference on Molecular Nanotechnology,
Nov 1990.
|
| @inproceedings{goldstein-foresight01,
author = {Goldstein, Seth Copen and Ellenbogen, James and Almassiam,
David and Brown, Matt and Cannarsa, Mark and Klein, Jesse and
Schell, Schuyler and Washburn, Geoff and Ziegler, Matthew M},
title = {MolSpice: Designing Molecular Logic Circuits},
booktitle = {Ninth Foresight Conference on Molecular
Nanotechnology},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-foresight01.pdf},
year = {2001},
month = {Nov},
address = {Santa Clara, CA},
keywords = {Electronic Nanotechnology, Molecular Electronics, CAD},
}
|
|
NanoFabrics: Extending Moore's Law Beyond the CMOS Era | pdf bib | |
Seth Copen Goldstein.
In The 10th International Conference on Architectural Support for Programming Languages and Operating Systems. (ASPLOS 'IX),
Nov 1990.
|
| @inproceedings{goldstein-asplos00,
title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
booktitle = {The 10th International Conference on Architectural
Support for Programming Languages and Operating Systems. (ASPLOS
'IX)},
author = {Goldstein, Seth Copen},
address = {Cambridge, MA},
year = {2000},
month = {Nov},
keywords = {Electronic Nanotechnology,Fault and Defect
Tolerance,Molecular Electronics,Reconfigurable Computing},
}
|
Memory Density |
|
Nonphotolithographic Nanoscale Memory Density Prospects | pdf bib | |
Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln.
IEEE Transactions on Nanotechnology,
volume 4, pages 215–228, Mar 1990.
|
| @article{lincoln-tnano05,
title = {Nonphotolithographic Nanoscale Memory Density Prospects},
abstract = {Technologies are now emerging to construct
molecular-scale electronic wires and switches using bottom-up
self-assembly. This opens the possibility of constructing
nanoscale circuits and memories where active devices are just a
few nanometers square and wire pitches may be on the order of ten
nanometers. The features can be defined at this scale without
using photolithography. The available assembly techniques have
relatively high defect rates compared to conventional
lithographic integrated circuits and can only produce very
regular structures. Nonetheless, with proper memory organization,
it is reasonable to expect these technologies to provide memory
densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
power requirements under 0.6 W/Tb/s for random read operations.},
url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
journal = {IEEE Transactions on Nanotechnology},
author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
and Lincoln, Patrick},
year = {2005},
month = {Mar},
volume = {4},
issue = {2},
pages = {215-228},
keywords = {Fault and Defect Tolerance, electronic nanotechnology,
memory density, memory organization, molecular electronics},
doi = {10.1109/TNANO.2004.837849},
}
|
Back to publications list
|