A High-Performance Flexible Architecture for Cryptography

@inproceedings{mahim-asplos06,
  title = {Tartan: Evaluating Spatial Computation for Whole Program
     Execution},
  author = {Mishra, Mahim and Callahan, Timothy J and Chelcea, Tiberiu
     and Venkataramani, Girish and Budiu, Mihai and Goldstein, Seth
     Copen},
  booktitle = {12th ACM International Conference on Architecture
     Support for Programming Languages and Operating Systems
     (ASPLOS)},
  year = {2006},
  pages = {163--174},
  address = {San Jose, CA},
  month = {Oct},
  abstract = {Spatial Computing (SC) has been shown to be an
     energy-efficient model for implementing program kernels. In this
     paper we explore the feasibility of using SC for more than small
     kernels. To this end, we evaluate the performance and energy
     efficiency of entire applications on Tartan, a general-purpose
     architecture which integrates a reconfigurable fabric (RF) with a
     superscalar core. Our compiler automatically partitions and
     compiles an application into an instruction stream for the core
     and a configuration for the RF. We use a detailed simulator to
     capture both timing and energy numbers for all parts of the
     system. \par Our results indicate that a hierarchical RF
     architecture, designed around a scalable interconnect, is
     instrumental in harnessing the benefits of spatial computation.
     The interconnect uses static configuration and routing at the
     lower levels and a packet-switched, dynamically-routed network at
     the top level. Tartan is most energy-efficient when almost all of
     the application is mapped to the RF, indicating the need for the
     RF to support most general-purpose programming constructs. Our
     initial investigation reveals that such a system can provide, on
     average, an order of magnitude improvement in energy-delay
     compared to an aggressive superscalar core on single-threaded
     workloads.},
  keywords = {Asychronous Circuits, Spatial Computing, Reconfigurable
     Computing,Phoenix, Tartan},
  url = {http://www.cs.cmu.edu/~seth/papers/mahim-asplos06.pdf},
}

@inproceedings{goldstein04-ersa04,
  author = {Goldstein, Seth Copen},
  title = {Computing Without Processors},
  booktitle = {International Conference on Engineering of
     Reconfigurable Systems and Algorithms (ERSA'04)},
  abstract = {The continuation of the remarkable exponential increases
     in processing power over the recent past faces imminent
     challenges due in part rising cost of design and manufacturing
     and the physics of deep-submicron semiconductor devices. In this
     talk we will discuss a promising alternative to ever more complex
     processors, application specific hardware (ASH). The ASH model is
     based on compiling high-level programs directly into circuits,
     which can either be fabricated as ASICs or more reasonably
     converted in configurations for reconfigurable devices. We will
     discuss the challenges involved in compiling sequential
     programming languages into circuits and the challenges in
     implementing those circuits in a scalable and power efficient
     manner.},
  address = {Las Vegas, NV},
  month = {Jun},
  year = {2004},
  pages = {29--32},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology,
     Fault and Defect Tolerance},
}

@incollection{mishra-nqmc04,
  title = {Defect Tolerance at the End of the Roadmap},
  booktitle = {Nano, Quantum and Molecular Computing: Implications to
     High Level Design and Validation},
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  year = {2004},
  editor = {Sandeep K. Shukla and R. Iris Bahar},
  publisher = {Kluwer Academic Publishers},
  isbn = {1-4020-80670},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Reconfigurable Computing,Phoenix,molecular
     electronics},
}

@inproceedings{budiu-async04,
  title = {Translating ANSI C to Asynchronous Circuits},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
  booktitle = {10th IEEE International Symposium on Asynchronous
     Circuits and Systems (ASYNC '04)},
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  address = {Crete, Greece},
  year = {2004},
  month = {Apr},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
     Computing},
}

@inproceedings{mishra-itsw03,
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  title = {Defect Tolerance After the Roadmap},
  booktitle = {Proceedings of the 10th International Test Synthesis
     Workshop (ITSW)},
  month = {Mar},
  year = {2003},
  address = {Santa Barbara, {CA}},
  keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
     Fault and Defect Tolerance},
  url = {http://www.cs.cmu.edu/~seth/papers/mishra-itsw03.pdf},
}

@inproceedings{mishra-itc03,
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  title = {Defect Tolerance at the End of the Roadmap},
  booktitle = {Proceedings of the International Test Conference
     ({ITC}), 2003},
  month = {Sep},
  year = {2003},
  address = {Charlotte, {NC}},
  url = {http://www.cs.cmu.edu/~seth/papers/mishra-itc03.pdf},
  abstract = {Defect tolerance will become more important as feature
     sizes shrink closer to single digit nanometer dimensions. This is
     true whether the chips are manufactured using top-down methods
     (e.g., photolithography) or bottom-up methods (e.g., chemically
     assembled electronic nanotechnology, or CAEN). In this paper, we
     propose a defect tolerance methodology centered around
     reconfigurable devices, a scalable testing method, and dynamic
     place-and-route. Our methodology is particularly well suited for
     CAEN.},
  keywords = {Spatial Computing, Reconfigurable
     Computing,Phoenix,Fault and Defect Tolerance},
}

@incollection{goldstein-mn03,
  title = {Molecules, Gates, Circuits, Computer},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
  booktitle = {Molecular Nanoelectronics},
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  year = {2003},
  editor = {Mark A. Reed and Takhee Lee},
  publisher = {American Scientific Publishers},
  address = {Stevenson Ranch, CA},
  month = {Jan},
  isbn = {1-588883-006-3},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Reconfigurable Computing,Spatial
     Computing,electronic nanotechnology,molecular electronics},
}

@inproceedings{budiu-cgo03,
  title = {Optimizing Memory Accesses For Spatial Computation},
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  booktitle = {Proceedings of the 1st International ACM/IEEE Symposium
     on Code Generation and Optimization (CGO 03)},
  year = {2003},
  address = {San Francisco, CA},
  month = {Mar},
  pages = {216-227},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-cgo03.pdf},
  keywords = {Spatial Computing, Reconfigurable
     Computing,Phoenix,Compilers:Memory Optimizations},
}

@inproceedings{goldstein-asap03,
  title = {Reconfigurable Computing and Electronic Nanotechnology},
  author = {Goldstein, Seth Copen and Budiu, Mihai and Mishra, Mahim
     and Venkataramani, Girish},
  booktitle = {Proceedings of the {IEEE} 14th International Conference
     on Application-specific Systems, Architectures and Processors
     ({ASAP} 2003)},
  year = {2003},
  address = {The Hague, Netherlands},
  month = {Jun},
  note = {Invited paper},
  pages = {132-143},
  abstract = {In this paper we examine the opportunities brought about
     by recent progress in electronic nanotechnology and describe the
     methods needed to harness them for building a new computer
     architecture. In this process we decompose some traditional
     abstractions, such as the transistor, into fine-grain pieces,
     such as signal restoration and input-output isolation. We also
     show how we can forgo the extreme reliability of CMOS circuits
     for low-cost chemical self-assembly at the expense of large
     manufacturing defect densities. We discuss advanced testing
     methods which can be used to recover perfect functionality from
     unreliable parts. We proceed to show how the molecular switch,
     the regularity of the circuits created by self-assembly and the
     high defect densities logically require the use of reconfigurable
     hardware as a basic building block for hardware design. We then
     capitalize on the convergence of compilation and hardware
     synthesis (which takes place when programming reconfigurable
     hardware) to propose the complete elimination of the
     instruction-set architecture from the system architecture, and
     the synthesis of asynchronous dataflow machines directly from
     high-level programming languages, such as C. We discuss in some
     detail a scalable compilation system that perform this task.},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asap03.pdf},
}

@inproceedings{goldstein-hldvt03,
  title = {Reconfigurable Nanoelectronics and Defect Tolerance},
  author = {Goldstein, Seth Copen},
  booktitle = {Proceedings of High-level design, verification, and
     test},
  year = {2003},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology,
     Fault and Defect Tolerance},
}

@inproceedings{venkataramani-fpl02,
  title = {Factors Influencing the Performance of a CPU-RFU Hybrid
     Architecture},
  author = {Venkataramani, Girish and Sudhir, Suraj and Budiu, Mihai
     and Goldstein, Seth Copen},
  booktitle = {Proceedings of the 12th International Conference on
     Field Programmable Logic and Applications (FPL)},
  year = {2002},
  address = {Montpellier (La Grande-Motte), France},
  month = {Sep},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-fpl02.pdf},
  abstract = {Closely coupling a reconfigurable fabric with a
     conventional processor has been shown to successfully improve the
     system performance. However, today s superscalar pro-cessors are
     both complex and adept at extracting Instruction Level
     Parallelism (ILP), which introduces many complex issues to the
     design of a hybrid CPU-RFU system. This paper examines the design
     of a superscalar processor augmented with a closely-coupled
     recon-figurable fabric. It identifies architectural and compiler
     issues that affect the performance of the overall system.
     Previous efforts at combining a processor core with a
     reconfigurable fabric are examined in the light of these issues.
     We also present simulation results that emphasize the impact of
     these factors.},
  pages = {955-965},
  isbn = {3-540-44108-5},
  publisher = {Springer-Verlag},
  keywords = {Spatial Computing,Reconfigurable Computing,Phoenix},
}

@inproceedings{yan-fccm02,
  author = {Yan, Rong and Goldstein, Seth Copen},
  title = {Memory: Improving Memory Locality in Very Large
     Reconfigurable Fabrics},
  booktitle = {Proceedings of 2002 IEEE Symposium on
     Field-Programmable Custom Computing Machines (FCCM)},
  year = {2002},
  address = {Napa Valley, CA},
  month = {Apr},
  url = {http://www.cs.cmu.edu/~seth/papers/yan-fccm02.pdf},
  keywords = {Reconfigurable Computing},
}

@inproceedings{butts-iccad02,
  title = {Molecular electronics: devices, systems and tools for
     gigagate,gigabit chips},
  url = {http://www.cs.cmu.edu/~seth/papers/butts-iccad02.pdf},
  doi = {http://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167569},
  booktitle = {International Conference on Computer-Aided Design (
     ICCAD '02)},
  author = {Butts, Michael and DeHon, Andre and Goldstein, Seth
     Copen},
  abstract = {New electronics technologies are emerging which may
     carry us beyond the limits of lithographic processing down to
     molecular-scale feature sizes. Devices and interconnects can be
     made from a variety of molecules and materials including bistable
     and switchable organic molecules, carbon nanotubes, and,
     single-crystal semiconductor nanowires. They can be
     self-assembled into organized structures and attached onto
     lithographic substrates. This tutorial reviews emerging
     molecular-scale electronics technology for CAD and system
     designers and highlights where ICCAD research can help support
     this technology.},
  address = {San Jose, CA},
  year = {2002},
  pages = {433-440},
  note = {invited tutorial at},
  month = {Nov},
  keywords = {Electronic Nanotechnology,Reconfigurable
     Computing,molecular electronics},
}

@inproceedings{budiu-fccm02,
  author = {Budiu, Mihai and Mishra, Mahim and Bharambe, Ashwin and
     Goldstein, Seth Copen},
  title = {Peer-to-peer Hardware-Software Interfaces for
     Reconfigurable Fabrics},
  booktitle = {Proceedings of 2002 IEEE Symposium on
     Field-Programmable Custom Computing Machines (FCCM)},
  year = {2002},
  month = {Apr},
  pages = {57-66},
  address = {Napa Valley, CA},
  abstract = {In this paper we describe a peer-to-peer interface
     between processor cores and reconfigurable fabrics. The main
     advantage of the peer-to-peer model is that it greatly expands
     the scope of application for reconfigurable computing and hence
     its potential benefits. The primary extension in our model is
     that ``code'' on the reconfigurable hardware unit is allowed to
     invoke routines both on the reconfigurable unit itself and on the
     fixed logic processor. We describe the software constructs and
     compilation mechanisms needed for such an architecture, including
     a detailed description of the interface between the two parts of
     the application.},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-fccm02.pdf},
  keywords = {Reconfigurable Computing},
}

@techreport{budiu-tr02,
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  title = {Pegasus: An Efficient Intermediate Representation},
  institution = {Carnegie Mellon University},
  year = {2002},
  number = {CMU-CS-02-107},
  month = {May},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr02.pdf},
  pages = {20},
  abstract = {We present Pegasus, a compact and expressive
     intermediate representation for imperative languages. The
     representation is suitable for target architectures supporting
     predicated execution and aggressive speculation. In Pegasus
     information about the global dataflow of the program is encoded
     in local structures, enabling compact and efficient algorithms
     for program optimizations. As a proof of the versatility of
     Pegasus, we have used it in a compiler translating C programs to
     hardware implementations.},
  keywords = {Spatial Computing, Reconfigurable Computing,Phoenix},
}

@inproceedings{mishra_goldstein_nsc1,
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  title = {Scalable Defect Tolerance for Molecular Electronics},
  booktitle = {Proceedings of the 1st Workshop on Non-Silicon
     Computing (NSC-1)},
  address = {{Cambridge, MA}},
  year = {2002},
  url = {http://www.cs.cmu.edu/~seth/papers/mishra_goldstein_nsc1.pdf},
  abstract = {Chemically assembled electronic nanotechnology (CAEN) is
     a promising alternative to CMOS-based computing. However,
     CAEN-based circuits are expected to have huge defect densities.
     To solve this problem CAEN can be used to build reconfigurable
     fabrics which, assuming the defects can be found, are inherently
     defect tolerant. In this paper, we propose a scalable testing
     methodology for finding defects in reconfigurable devices.},
  keywords = {Reconfigurable Computing, Phoenix,Fault and Defect
     Tolerance},
}

@inproceedings{sudhir-fpl01,
  author = {Sudhir, Suraj and Nath, Suman and Goldstein, Seth Copen},
  title = {Configuration Caching and Swapping},
  year = {2001},
  booktitle = {11th International Conference on Field Programmable
     Logic and Applications},
  address = {Belfast, Northern Ireland},
  month = {Aug},
  keywords = {Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/sudhir-fpl01.pdf},
}

@inproceedings{goldstein-wvlsi01,
  title = {Electronic Nanotechnology and Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-wvlsi01.pdf},
  booktitle = {Proceedings of the IEEE Computer Society Workshop VLSI
     2001},
  author = {Goldstein, Seth Copen},
  year = {2001},
  pages = {10},
  month = {Apr},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Reconfigurable Computing},
}

@inproceedings{cadambi-fpl01,
  title = {Static Profile-driven Compilation for FPGAs},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpl01.pdf},
  booktitle = {Proceedings of the 11th International Conference on
     Field-Programmable Logic and Applications},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  address = {Belfast, Northern Ireland},
  year = {2001},
  month = {Aug},
  keywords = {CAD,Reconfigurable Computing},
}

@inproceedings{goldstein-isca01,
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  title = {{NanoFabrics}: Spatial Computing Using Molecular
     Electronics},
  booktitle = {Proceedings of the 28th International Symposium on
     Computer Architecture (ISCA)},
  month = {Jul},
  address = {{G\"{o}teborg, Sweden}},
  year = {2001},
  pages = {178--189},
  abstract = {The continuation of the remarkable exponential increases
     in processing power over the recent past faces imminent
     challenges due in part to the physics of deep-submicron CMOS
     devices and the costs of both chip masks and future fabrication
     plants. A promising solution to these problems is offered by an
     alternative to CMOS-based computing, chemically assembled
     electronic nanotechnology (CAEN). In this paper we outline how
     CAEN based computing can become a reality. We briefly describe
     recent work in CAEN and how CAEN will affect computer
     architecture. We show how the inherently reconfigurable natures
     of CAEN devices can be exploited to provide high-density chips
     with defect tolerance which will significantly reduce the cost of
     manufacturing. After developing the basic building blocks of a
     CAEN based computing devices we present some preliminary results
     which indicate that CAEN based computing devices can meet or
     exceed the performance of CMOS based devices.},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca01.pdf},
  keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
     Electronic Nanotechnology},
}

@techreport{budiu-tr00,
  title = {BitValue Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr00.pdf},
  booktitle = {CMU CS Technical Report, CMU-CS-00-141},
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  institution = {Carnegie Mellon University},
  year = {2000},
  month = {Jun},
  see = {budiu-europar00},
  keywords = {CAD,Compilers:CASH,Reconfigurable Computing},
}

@inproceedings{walker-fccm00,
  author = {Walker, Kevin and Budiu, Mihai and Goldstein, Seth Copen},
  title = {Interfacing Reconfigurable Logic with a {CPU}},
  booktitle = {2000 IEEE Symposium on Field-Programmable Custom
     Computing Machines},
  pages = {317--318},
  year = {2000},
  url = {http://www.cs.cmu.edu/~seth/papers/walker-fccm00.pdf},
  abstract = {Reconfigurable computing devices have achieved
     substantial performance improvements over conventional processors
     on some computational kernels. These benefits derive from
     hardware customization which avoids the mismatch between the
     basic requirements of the algorithms and the architectures of the
     processors. A reconfigurable fabric alone is not sufficient for
     general-purpose computing since it can be ill-suited to executing
     entire programs due to space limitations, dataflow-centricity,
     and inefficiency at implementing some operations (e.g.
     floating-point arithmetic). These observations have led to the
     appearance of numerous designs which place some form of
     reconfigurable logic under the control of a general-purpose
     processor. The authors explore the ways in which a reconfigurable
     fabric can be interfaced with a general-purpose processor. While
     off-chip reconfigurable fabrics have proven to be quite effective
     at performing streaming, data-intensive computations, they
     require large streams of data to overcome the latency between the
     devices. We explore the design space for an on-chip fabric, i.e.,
     a reconfigurable function unit (RFU). An RFU allows smaller
     portions of application to be mapped to the fabric in the form of
     custom instructions. Though the speedups achieved for stream
     based computations will in general be much larger than those for
     custom instructions, they are limited to a smaller class of
     applications. Custom instructions, however, can be found in a
     larger class of programs, and compiler techniques can
     automatically create them.},
  keywords = {Reconfigurable Computing},
}

@inproceedings{goldstein-asplos00,
  title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
  booktitle = {The 10th International Conference on Architectural
     Support for Programming Languages and Operating Systems. (ASPLOS
     'IX)},
  author = {Goldstein, Seth Copen},
  address = {Cambridge, MA},
  year = {2000},
  month = {Nov},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Molecular Electronics,Reconfigurable Computing},
}

@incollection{schmit-fpcct00,
  title = {Pipeline Reconfigurable FPGAs},
  url = {http://www.cs.cmu.edu/~seth/papers/schmit-fpcct00.pdf},
  booktitle = {Field-Programmable Custom Computing Technology:
     Architecture, Tools, and Applications},
  author = {Schmit, Herman and Goldstein, Seth Copen and Cadambi,
     Srihari and Moe, Matthew},
  year = {2000},
  editor = {Arnold, Jeffrey and Luk, Wayne and Pocek, Ken},
  publisher = {Kluwer Academic Publishers},
  isbn = {0-7923-7803-2},
  keywords = {PipeRench,Reconfigurable Computing},
}

@article{schmit-jvlsi00,
  author = {Schmit, Herman and Cadambi, Srihari and Moe, Matthew and
     Goldstein, Seth Copen},
  title = {Pipeline Reconfigurable FPGAs},
  journal = {Journal of VLSI Signal Processing Systems},
  volume = {33},
  month = {Apr},
  year = {2000},
  pages = {70-77},
  abstract = {While reconfigurable computing promises to deliver
     incomparable performance, it is still a marginal technology due
     to the high cost of developing and upgrading applications.
     Hardware virtualization can be used to significantly reduce both
     these costs. In this paper we describe the benefits of hardware
     virtualization, and show how it can be achieved using the
     technique of pipeline reconfiguration. The result is PipeRench,
     an architecture that supports robust compilation and provides
     forward compatibility. Our preliminary performance analysis on
     PipeRench predicts that it will outperform commercial FPGAs and
     DSPs in both overall performance and in performance normalized
     for silicon area over a broad range of problem sizes.},
  number = {4},
  url = {http://www.cs.cmu.edu/~seth/papers/schmit-jvlsi00.pdf},
  doi = {},
  also = {chapter in Field-Programmable Custom Computing Technology:
     Architecture, Tools, and Applications},
  keywords = {PipeRench,Reconfigurable Computing},
}

@inproceedings{sinha-fccm00,
  title = {Tunable Fault Tolerance for Runtime Reconfigurable
     Architectures},
  url = {http://www.cs.cmu.edu/~seth/papers/sinha-fccm00.pdf},
  booktitle = {8th IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM 2000)},
  author = {Sinha, Steven K. and Kamarchik, Peter M. and Goldstein,
     Seth Copen},
  abstract = {Fault tolerance is becoming an increasingly important
     issue, especially in mission-critical applications where data
     integrity is a paramount concern. Performance, however, remains a
     large driving force in the market place. Runtime reconfigurable
     hardware architectures have the power to balance fault tolerance
     with performance, allowing the amount of fault tolerance to be
     tuned at run-time. This paper describes a new built-in self-test
     designed to run on, and take advantage of, runtime reconfigurable
     architectures using the PipeRench architecture as a model. In
     addition, this paper introduces a new metric by which a user can
     set the desired fault tolerance of a runtime reconfigurable
     device},
  doi = {10.1109/FPGA.2000.903405},
  year = {2000},
  pages = {185-192},
  isbn = {0-7695-0871-5},
  address = {Napa Valley, CA},
  month = {Apr},
  keywords = {Fault And Defect Tolerance,PipeRench,Reconfigurable
     Computing},
}

@inproceedings{budiu-europar00,
  title = {{BitValue} Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  author = {Budiu, Mihai and Sakr, Majd and Walker, Kevin and
     Goldstein, Seth Copen},
  booktitle = {Proceedings of the 2000 Europar Conference},
  year = {2000},
  volume = {1900},
  pages = {969--979},
  month = {Aug},
  issn = {0302-9743},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer Verlag},
  address = {Munich, Germany},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-europar00.pdf},
  also = {CMU CS Technical Report, CMU-CS-00-141, October 2000.},
  abstract = {We present a compiler algorithm called BitValue, which
     can discover both unused and constant bits in dusty-deck C
     programs. BitValue uses forward and backward dataflow analyses,
     generalizing constant-folding and dead-code detection at the
     bit-level. This algorithm enables compiler optimizations which
     target special processor architectures for computing on
     non-standard bitwidths. Using this algorithm we show that up to
     31\% of the computed bytes are thrown away (for programs from
     SpecINT95 and Mediabench). A compiler for reconfigurable hardware
     uses this algorithm to achieve substantial reductions (up to
     20-fold) in the size of the synthesized circuits.},
  keywords = {Spatial Computing,Reconfigurable
     Computing,Phoenix,PipeRench,CAD},
}

@article{goldstein-ieee00,
  author = {Goldstein, Seth Copen and Schmit, Herman and Budiu, Mihai
     and Cadambi, Srihari and Moe, Matthew and Taylor, R. Reed},
  title = {{PipeRench}: A Reconfigurable Architecture and Compiler},
  journal = {IEEE Computer},
  year = {2000},
  volume = {33},
  number = {4},
  month = {Apr},
  pages = {70--77},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-ieee00.pdf},
  abstract = {With the proliferation of highly specialized embedded
     computer systems has come a diversification of workloads for
     computing devices. General-purpose processors are struggling to
     efficiently meet these applications' disparate needs, and custom
     hardware is rarely feasible. According to the authors,
     reconfigurable computing, which combines the flexibility of
     general-purpose processors with the efficiency of custom
     hardware, can provide the alternative. PipeRench and its
     associated compiler comprise the authors' new architecture for
     reconfigurable computing. Combined with a traditional digital
     signal processor, microcontroller or general-purpose processor,
     PipeRench can support a system's various computing needs without
     requiring custom hardware. The authors describe the PipeRench
     architecture and how it solves some of the pre-existing problems
     with FPGA architectures, such as logic granularity, configuration
     time, forward compatibility, hard constraints and compilation
     time.},
  keywords = {Reconfigurable Computing,PipeRench},
}

@inproceedings{reed-ches99,
  author = {Taylor, R. Reed and Goldstein, Seth Copen},
  title = {A High-Performance Flexible Architecture for Cryptography},
  booktitle = {Proceedings of the Workshop on Cryptographic Hardware
     and Embedded Systems 1999 (CHES99)},
  address = {Worcester, MA},
  year = {1999},
  pages = {231-245},
  month = {Aug},
  abstract = {Cryptographic algorithms are more efficiently
     implemented in custom hardware than in software running on
     general-purpose processors. However, systems which use hardware
     implementations have significant drawbacks: they are unable to
     respond to flaws discovered in the implemented algorithm or to
     changes in standards. In this paper we show how reconfigurable
     computing offers high performance yet flexible solutions for
     cryptographic algorithms. We focus on PipeRench, a reconfigurable
     fabric that supports implementations which can yield better than
     custom-hardware performance and yet maintains all the flexibility
     of software based systems. PipeRench is a pipelined
     reconfigurable fabric which virtualizes hardware, enabling large
     circuits to be run on limited physical hardware. We present
     implementations for Crypton, IDEA, RC6, and Twofish on PipeRench
     and an extension of PipeRench, PipeRench+. We also describe how
     various proposed AES algorithms could be implemented on
     PipeRench. PipeRench achieves speedups of between 2x and 12x over
     conventional processors.},
  url = {http://www.cs.cmu.edu/~seth/papers/reed-ches99.pdf},
  keywords = {PipeRench,Reconfigurable Computing},
}

@inproceedings{cadambi-fccm99,
  title = {CPR: A Configuration Profiling Tool},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fccm99.pdf},
  booktitle = {7th Annual IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM '99)},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  year = {1999},
  pages = {104},
  address = {Napa Valley, CA},
  month = {Apr},
  keywords = {CAD,Reconfigurable Computing,Place And Route},
}

@inproceedings{budiu-fpga99,
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  title = {Fast Compilation for Pipelined Reconfigurable Fabrics},
  booktitle = {Proceedings of the 1999 ACM/SIGDA Seventh International
     Symposium on Field Programmable Gate Arrays (FPGA '99)},
  month = {Feb},
  year = {1999},
  pages = {195-205},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-fpga99.pdf},
  abstract = {In this paper we describe a compiler which quickly
     synthesizes high quality pipelined datapaths for pipelined
     reconfigurable devices. The compiler uses the same internal
     representation to perform synthesis, module generation,
     optimization, and place and route. The core of the compiler is a
     linear time place and route algorithm more than two orders of
     magnitude faster than traditional CAD tools. The key behind our
     approach is that we never backtrack, rip-up, or re-route.
     Instead, the graph representing the computation is preprocessed
     to guarantee routability by inserting lazy noops. The
     preprocessing steps provides enough information to make a greedy
     strategy feasible. The compilation speed is approximately 3000
     bit-operations/second (on a PII/400Mhz) for a wide range of
     applications. The hardware utilization averages 60\% on the
     target device, PipeRench.},
  keywords = {Reconfigurable Computing,PipeRench,Place and Route},
}

@inproceedings{goldstein-isca99,
  author = {Goldstein, Seth Copen and Schmit, Herman and Moe, Matthew
     and Budiu, Mihai and Cadambi, Srihari and Taylor, R. Reed and
     Laufer, Ronald},
  title = {{PipeRench}: a Coprocessor for Streaming Multimedia
     Acceleration},
  booktitle = {Proceedings of the 26th International Symposium on
     Computer Architecture (ISCA)},
  month = {May},
  year = {1999},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca99.pdf},
  pages = {28--39},
  abstract = {Future computing workloads will emphasize an
     architecture's ability to perform relatively simple calculations
     on massive quantities of mixed-width data. This paper describes a
     novel reconfigurable fabric architecture, PipeRench, optimized to
     accelerate these types of computations. PipeRench enables fast,
     robust compilers, supports forward compatibility, and virtualizes
     configurations, thus removing the fixed size constraint present
     in other fabrics. For the first time we explore how the bit-width
     of processing elements affects performance and show how the
     PipeRench architecture has been optimized to balance the needs of
     the compiler against the realities of silicon. Finally, we
     demonstrate extreme performance speedup on certain computing
     kernels (up to 190x versus a modern RISC processor), and analyze
     how this acceleration translates to application speedup.},
  address = {Atlanta, GA},
  keywords = {Reconfigurable Computing,PipeRench},
}

@inproceedings{moe-fccm98,
  author = {Moe, Matthew and Schmit, Herman and Goldstein, Seth
     Copen},
  title = {{Characterization and Parameterization of a Pipeline
     Reconfigurable {FGPA}}},
  booktitle = {6th Annual IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM '98)},
  month = {Apr},
  address = {Napa, CA},
  year = {1998},
  pages = {294--295},
  note = {poster session 3},
  keywords = {PipeRench, Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/moe-fccm98.pdf},
}

@inproceedings{cadambi-fpga98,
  author = {Cadambi, Srihari and Weener, J. and Goldstein, Seth Copen
     and Schmit, Herman and Thomas, Donald E},
  title = {{Managing pipeline-reconfigurable FPGAs}},
  booktitle = {Proceedings of the 1998 ACM/SIGDA Sixth International
     Symposium on Field Programmable Gate Arrays},
  year = {1998},
  month = {Feb},
  pages = {55--64},
  address = {Monterey, CA},
  abstract = {While reconfigurable computing promises to deliver
     incomparable performance, it is still a marginal technology due
     to the high cost of developing and upgrading applications.
     Hardware virtualization can be used to significantly reduce both
     these costs. In this paper we describe the benefits of hardware
     virtualization, and show how it can be acheived using a
     combination of pipeline reconfiguration and run-time scheduling
     of both configuration streams and data streams. The result is
     PipeRench, an architecture that supports robust compilation and
     provides forward compatibility. Our preliminary performance
     analysis predicts that PipeRench will outperform commercial FPGAs
     and DSPs in both overall performance and in performance per
     mm$^2$.},
  keywords = {PipeRench, Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpga98.pdf},
}

@inproceedings{KSS00,
  author = {Kamarchik, Peter M. and Sinha, Steven and Goldstein, Seth
     Copen},
  title = {Fault Tolerance in Run-time Reconfigurable Architectures},
  booktitle = {IEEE Symposium on FPGAs for Custom Computing Machines
     (FCCM '00)},
  year = {2000},
  month = {Apr},
  address = {Napa, CA},
  keywords = {PipeRench, Fault and Defect Tolerance},
}

@incollection{schmit-fpcct00,
  title = {Pipeline Reconfigurable FPGAs},
  url = {http://www.cs.cmu.edu/~seth/papers/schmit-fpcct00.pdf},
  booktitle = {Field-Programmable Custom Computing Technology:
     Architecture, Tools, and Applications},
  author = {Schmit, Herman and Goldstein, Seth Copen and Cadambi,
     Srihari and Moe, Matthew},
  year = {2000},
  editor = {Arnold, Jeffrey and Luk, Wayne and Pocek, Ken},
  publisher = {Kluwer Academic Publishers},
  isbn = {0-7923-7803-2},
  keywords = {PipeRench,Reconfigurable Computing},
}

@article{schmit-jvlsi00,
  author = {Schmit, Herman and Cadambi, Srihari and Moe, Matthew and
     Goldstein, Seth Copen},
  title = {Pipeline Reconfigurable FPGAs},
  journal = {Journal of VLSI Signal Processing Systems},
  volume = {33},
  month = {Apr},
  year = {2000},
  pages = {70-77},
  abstract = {While reconfigurable computing promises to deliver
     incomparable performance, it is still a marginal technology due
     to the high cost of developing and upgrading applications.
     Hardware virtualization can be used to significantly reduce both
     these costs. In this paper we describe the benefits of hardware
     virtualization, and show how it can be achieved using the
     technique of pipeline reconfiguration. The result is PipeRench,
     an architecture that supports robust compilation and provides
     forward compatibility. Our preliminary performance analysis on
     PipeRench predicts that it will outperform commercial FPGAs and
     DSPs in both overall performance and in performance normalized
     for silicon area over a broad range of problem sizes.},
  number = {4},
  url = {http://www.cs.cmu.edu/~seth/papers/schmit-jvlsi00.pdf},
  doi = {},
  also = {chapter in Field-Programmable Custom Computing Technology:
     Architecture, Tools, and Applications},
  keywords = {PipeRench,Reconfigurable Computing},
}

@inproceedings{sinha-fccm00,
  title = {Tunable Fault Tolerance for Runtime Reconfigurable
     Architectures},
  url = {http://www.cs.cmu.edu/~seth/papers/sinha-fccm00.pdf},
  booktitle = {8th IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM 2000)},
  author = {Sinha, Steven K. and Kamarchik, Peter M. and Goldstein,
     Seth Copen},
  abstract = {Fault tolerance is becoming an increasingly important
     issue, especially in mission-critical applications where data
     integrity is a paramount concern. Performance, however, remains a
     large driving force in the market place. Runtime reconfigurable
     hardware architectures have the power to balance fault tolerance
     with performance, allowing the amount of fault tolerance to be
     tuned at run-time. This paper describes a new built-in self-test
     designed to run on, and take advantage of, runtime reconfigurable
     architectures using the PipeRench architecture as a model. In
     addition, this paper introduces a new metric by which a user can
     set the desired fault tolerance of a runtime reconfigurable
     device},
  doi = {10.1109/FPGA.2000.903405},
  year = {2000},
  pages = {185-192},
  isbn = {0-7695-0871-5},
  address = {Napa Valley, CA},
  month = {Apr},
  keywords = {Fault And Defect Tolerance,PipeRench,Reconfigurable
     Computing},
}

@inproceedings{budiu-europar00,
  title = {{BitValue} Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  author = {Budiu, Mihai and Sakr, Majd and Walker, Kevin and
     Goldstein, Seth Copen},
  booktitle = {Proceedings of the 2000 Europar Conference},
  year = {2000},
  volume = {1900},
  pages = {969--979},
  month = {Aug},
  issn = {0302-9743},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer Verlag},
  address = {Munich, Germany},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-europar00.pdf},
  also = {CMU CS Technical Report, CMU-CS-00-141, October 2000.},
  abstract = {We present a compiler algorithm called BitValue, which
     can discover both unused and constant bits in dusty-deck C
     programs. BitValue uses forward and backward dataflow analyses,
     generalizing constant-folding and dead-code detection at the
     bit-level. This algorithm enables compiler optimizations which
     target special processor architectures for computing on
     non-standard bitwidths. Using this algorithm we show that up to
     31\% of the computed bytes are thrown away (for programs from
     SpecINT95 and Mediabench). A compiler for reconfigurable hardware
     uses this algorithm to achieve substantial reductions (up to
     20-fold) in the size of the synthesized circuits.},
  keywords = {Spatial Computing,Reconfigurable
     Computing,Phoenix,PipeRench,CAD},
}

@article{goldstein-ieee00,
  author = {Goldstein, Seth Copen and Schmit, Herman and Budiu, Mihai
     and Cadambi, Srihari and Moe, Matthew and Taylor, R. Reed},
  title = {{PipeRench}: A Reconfigurable Architecture and Compiler},
  journal = {IEEE Computer},
  year = {2000},
  volume = {33},
  number = {4},
  month = {Apr},
  pages = {70--77},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-ieee00.pdf},
  abstract = {With the proliferation of highly specialized embedded
     computer systems has come a diversification of workloads for
     computing devices. General-purpose processors are struggling to
     efficiently meet these applications' disparate needs, and custom
     hardware is rarely feasible. According to the authors,
     reconfigurable computing, which combines the flexibility of
     general-purpose processors with the efficiency of custom
     hardware, can provide the alternative. PipeRench and its
     associated compiler comprise the authors' new architecture for
     reconfigurable computing. Combined with a traditional digital
     signal processor, microcontroller or general-purpose processor,
     PipeRench can support a system's various computing needs without
     requiring custom hardware. The authors describe the PipeRench
     architecture and how it solves some of the pre-existing problems
     with FPGA architectures, such as logic granularity, configuration
     time, forward compatibility, hard constraints and compilation
     time.},
  keywords = {Reconfigurable Computing,PipeRench},
}

@inproceedings{reed-ches99,
  author = {Taylor, R. Reed and Goldstein, Seth Copen},
  title = {A High-Performance Flexible Architecture for Cryptography},
  booktitle = {Proceedings of the Workshop on Cryptographic Hardware
     and Embedded Systems 1999 (CHES99)},
  address = {Worcester, MA},
  year = {1999},
  pages = {231-245},
  month = {Aug},
  abstract = {Cryptographic algorithms are more efficiently
     implemented in custom hardware than in software running on
     general-purpose processors. However, systems which use hardware
     implementations have significant drawbacks: they are unable to
     respond to flaws discovered in the implemented algorithm or to
     changes in standards. In this paper we show how reconfigurable
     computing offers high performance yet flexible solutions for
     cryptographic algorithms. We focus on PipeRench, a reconfigurable
     fabric that supports implementations which can yield better than
     custom-hardware performance and yet maintains all the flexibility
     of software based systems. PipeRench is a pipelined
     reconfigurable fabric which virtualizes hardware, enabling large
     circuits to be run on limited physical hardware. We present
     implementations for Crypton, IDEA, RC6, and Twofish on PipeRench
     and an extension of PipeRench, PipeRench+. We also describe how
     various proposed AES algorithms could be implemented on
     PipeRench. PipeRench achieves speedups of between 2x and 12x over
     conventional processors.},
  url = {http://www.cs.cmu.edu/~seth/papers/reed-ches99.pdf},
  keywords = {PipeRench,Reconfigurable Computing},
}

@inproceedings{budiu-fpga99,
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  title = {Fast Compilation for Pipelined Reconfigurable Fabrics},
  booktitle = {Proceedings of the 1999 ACM/SIGDA Seventh International
     Symposium on Field Programmable Gate Arrays (FPGA '99)},
  month = {Feb},
  year = {1999},
  pages = {195-205},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-fpga99.pdf},
  abstract = {In this paper we describe a compiler which quickly
     synthesizes high quality pipelined datapaths for pipelined
     reconfigurable devices. The compiler uses the same internal
     representation to perform synthesis, module generation,
     optimization, and place and route. The core of the compiler is a
     linear time place and route algorithm more than two orders of
     magnitude faster than traditional CAD tools. The key behind our
     approach is that we never backtrack, rip-up, or re-route.
     Instead, the graph representing the computation is preprocessed
     to guarantee routability by inserting lazy noops. The
     preprocessing steps provides enough information to make a greedy
     strategy feasible. The compilation speed is approximately 3000
     bit-operations/second (on a PII/400Mhz) for a wide range of
     applications. The hardware utilization averages 60\% on the
     target device, PipeRench.},
  keywords = {Reconfigurable Computing,PipeRench,Place and Route},
}

@inproceedings{goldstein-isca99,
  author = {Goldstein, Seth Copen and Schmit, Herman and Moe, Matthew
     and Budiu, Mihai and Cadambi, Srihari and Taylor, R. Reed and
     Laufer, Ronald},
  title = {{PipeRench}: a Coprocessor for Streaming Multimedia
     Acceleration},
  booktitle = {Proceedings of the 26th International Symposium on
     Computer Architecture (ISCA)},
  month = {May},
  year = {1999},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca99.pdf},
  pages = {28--39},
  abstract = {Future computing workloads will emphasize an
     architecture's ability to perform relatively simple calculations
     on massive quantities of mixed-width data. This paper describes a
     novel reconfigurable fabric architecture, PipeRench, optimized to
     accelerate these types of computations. PipeRench enables fast,
     robust compilers, supports forward compatibility, and virtualizes
     configurations, thus removing the fixed size constraint present
     in other fabrics. For the first time we explore how the bit-width
     of processing elements affects performance and show how the
     PipeRench architecture has been optimized to balance the needs of
     the compiler against the realities of silicon. Finally, we
     demonstrate extreme performance speedup on certain computing
     kernels (up to 190x versus a modern RISC processor), and analyze
     how this acceleration translates to application speedup.},
  address = {Atlanta, GA},
  keywords = {Reconfigurable Computing,PipeRench},
}

@inproceedings{blanton-ftc98,
  author = {Blanton, Shawn and Goldstein, Seth Copen and Schmit,
     Herman},
  title = {Tunable Fault Tolernace via Test and Reconfiguration},
  booktitle = {Digest of FastAbstracts of the 28th Annual
     International Symposium on Fault-Tolerant Computing},
  year = {1998},
  month = {Jun},
  pages = {9--10},
  keywords = {PipeRench, Fault and Defect Tolerance},
  url = {http://www.cs.cmu.edu/~seth/papers/blanton-ftc98.pdf},
}

@inproceedings{moe-fccm98,
  author = {Moe, Matthew and Schmit, Herman and Goldstein, Seth
     Copen},
  title = {{Characterization and Parameterization of a Pipeline
     Reconfigurable {FGPA}}},
  booktitle = {6th Annual IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM '98)},
  month = {Apr},
  address = {Napa, CA},
  year = {1998},
  pages = {294--295},
  note = {poster session 3},
  keywords = {PipeRench, Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/moe-fccm98.pdf},
}

@inproceedings{cadambi-fpga98,
  author = {Cadambi, Srihari and Weener, J. and Goldstein, Seth Copen
     and Schmit, Herman and Thomas, Donald E},
  title = {{Managing pipeline-reconfigurable FPGAs}},
  booktitle = {Proceedings of the 1998 ACM/SIGDA Sixth International
     Symposium on Field Programmable Gate Arrays},
  year = {1998},
  month = {Feb},
  pages = {55--64},
  address = {Monterey, CA},
  abstract = {While reconfigurable computing promises to deliver
     incomparable performance, it is still a marginal technology due
     to the high cost of developing and upgrading applications.
     Hardware virtualization can be used to significantly reduce both
     these costs. In this paper we describe the benefits of hardware
     virtualization, and show how it can be acheived using a
     combination of pipeline reconfiguration and run-time scheduling
     of both configuration streams and data streams. The result is
     PipeRench, an architecture that supports robust compilation and
     provides forward compatibility. Our preliminary performance
     analysis predicts that PipeRench will outperform commercial FPGAs
     and DSPs in both overall performance and in performance per
     mm$^2$.},
  keywords = {PipeRench, Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpga98.pdf},
}