Interfacing Reconfigurable Logic with a CPU

 

In 2000 IEEE Symposium on Field-Programmable Custom Computing Machines

Kevin Walker, Mihai Budiu, and Seth Copen Goldstein

pages 317–318

1990

Abstract

Reconfigurable computing devices have achieved substantial performance improvements over conventional processors on some computational kernels. These benefits derive from hardware customization which avoids the mismatch between the basic requirements of the algorithms and the architectures of the processors. A reconfigurable fabric alone is not sufficient for general-purpose computing since it can be ill-suited to executing entire programs due to space limitations, dataflow-centricity, and inefficiency at implementing some operations (e.g. floating-point arithmetic). These observations have led to the appearance of numerous designs which place some form of reconfigurable logic under the control of a general-purpose processor. The authors explore the ways in which a reconfigurable fabric can be interfaced with a general-purpose processor. While off-chip reconfigurable fabrics have proven to be quite effective at performing streaming, data-intensive computations, they require large streams of data to overcome the latency between the devices. We explore the design space for an on-chip fabric, i.e., a reconfigurable function unit (RFU). An RFU allows smaller portions of application to be mapped to the fabric in the form of custom instructions. Though the speedups achieved for stream based computations will in general be much larger than those for custom instructions, they are limited to a smaller class of applications. Custom instructions, however, can be found in a larger class of programs, and compiler techniques can automatically create them.

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@inproceedings{walker-fccm00,
  author = {Walker, Kevin and Budiu, Mihai and Goldstein, Seth Copen},
  title = {Interfacing Reconfigurable Logic with a {CPU}},
  booktitle = {2000 IEEE Symposium on Field-Programmable Custom
     Computing Machines},
  pages = {317--318},
  year = {2000},
  url = {http://www.cs.cmu.edu/~seth/papers/walker-fccm00.pdf},
  abstract = {Reconfigurable computing devices have achieved
     substantial performance improvements over conventional processors
     on some computational kernels. These benefits derive from
     hardware customization which avoids the mismatch between the
     basic requirements of the algorithms and the architectures of the
     processors. A reconfigurable fabric alone is not sufficient for
     general-purpose computing since it can be ill-suited to executing
     entire programs due to space limitations, dataflow-centricity,
     and inefficiency at implementing some operations (e.g.
     floating-point arithmetic). These observations have led to the
     appearance of numerous designs which place some form of
     reconfigurable logic under the control of a general-purpose
     processor. The authors explore the ways in which a reconfigurable
     fabric can be interfaced with a general-purpose processor. While
     off-chip reconfigurable fabrics have proven to be quite effective
     at performing streaming, data-intensive computations, they
     require large streams of data to overcome the latency between the
     devices. We explore the design space for an on-chip fabric, i.e.,
     a reconfigurable function unit (RFU). An RFU allows smaller
     portions of application to be mapped to the fabric in the form of
     custom instructions. Though the speedups achieved for stream
     based computations will in general be much larger than those for
     custom instructions, they are limited to a smaller class of
     applications. Custom instructions, however, can be found in a
     larger class of programs, and compiler techniques can
     automatically create them.},
  keywords = {Reconfigurable Computing},
}

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