Abstract: Our research group is working on formal verification techniques targeting C based VLSI design descriptions. Recently there has been a great deal of attention in the use of the C programming language (or its extensions) for describing hardware as well as software with the intention to support hardware-software co-design processes with a single language. Here we first discuss such design methodologies by which system level descriptions for hardware-software combined systems can be uniformly and smoothly refined into implementation in RTL for hardware and assembly languages for software. Starting from regular C programming language descriptions, the design methodologies repeat a number of small refinement steps and gradually add more and more details into the target designs. We also discuss formal verification of system level descriptions in those design methodologies from the viewpoint of formal verification. Since such descriptions have essential concurrency and C must be extended to be able to represent such concurrency, an effective and efficient formal verification of synchronization of concurrent processes is one of the most important issues in system level designs. We present model checking and equivalence checking methods targeting the design methodology that can check correctness of design descriptions with preliminary experimental results. The proposed formal verification methods will support the design methodologies and are very efficient by utilizing the fact that the design methodologies consist of lots of small refinement steps.

Thanyapat Sakunkonchak is a Postdoctoral Fellow at the University of Tokyo. He received a B.Eng. and an M.S. in Electrical Engineering from the Sirindhorn International Institute of Technology, Thailand, and a Ph.D. in Electronic Engineering from the University of Tokyo. His research interests include hardware and software verification, equivalence checking, and concurrent programming.