Masahiro Fujita:
Modular-HED: A Canonical Decision Diagram for Modular Equivalence Verification of Polynomial Functions and its Application to Synthesis and Verification of Arithmetic Circuits

Abstract: In this talk, we introduce a canonical polynomial representation called Modular Horner Expansion Diagram (Modular-HED) which is able to represent multi-variate polynomial functions over finite integer rings. This representation not only has a compact and canonical form, but also is close to hardware-software descriptions so that it can be utilized as a common model for formal verification as well as synthesis. This talk discusses how to reduce polynomial functions to normal forms in a canonical decision diagram. In order to evaluate the effectiveness of our approach, we apply the Modular-HED package to equivalence verification problem and compare experimental results with those of contemporary techniques. Also, we will discuss the use of Modular-HED and also bit-level analysis methods to optimize arithmetic circuits such as multipliers, MAC circuits, and others. The proposed techniques combine word-level and bit-level analysis so that both architectural and circuit level optimizations can be analyzed within the same framework. The proposed verification methods

Bio:
Masahiro Fujita received his Ph.D. from the University of Tokyo in 1985. He is a professor in VLSI Design and Education Center (VDEC) at the University of Tokyo. Prior to joining the University of Tokyo in 2000, he was director of CAD for VLSI in Fujitsu Laboratories of America for 6 years. He has done innovative works in the areas of digital design verification, synthesis, and testing. He has co-authored 7 books, and has over 100 publications. He has been given several research awards from Japanese scientific societies. His current research interests include synthesis and verification in higher level design stages, hardware/software co-designs and also digital/analog co-designs.

Appointments: dcm@cs.cmu.edu

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