The selective prefetching algorithm uses several compile-time parameters to model the behavior of the memory subsystem. Specifically these parameters include: (i) cache line size, (ii) whether unknown loop bounds are assumed to be large or small, (iii) effective cache size, and (iv) prefetch latency. The most concrete of these parameters is the cache line size, which is fixed given a specific architecture, and can be set precisely. The other parameters, however, are more heuristic in nature. For example, with a direct-mapped cache, the effective cache size is set to some value less than the actual cache size to model the effects of conflicts, but there is no precise method for determining this value. Similarly, the prefetch latency is set to some value larger than the latency of a memory access to model bandwidth-related delays, but this value is also somewhat arbitrary. To evaluate the robustness of our algorithm, we measured the effects of varying these less obvious parameters.