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You will be doing your Intro to Computer Systems (ICS) lab assignments
on a cluster of rack-mounted Intel Nehalem-based servers called the
shark machines. This cluster was donated by the Intel Labs
Higher Education group for the ICS course. The original 213
cluster machines were known as the fish machines. Our new
cluster systems are much bigger and faster, so it seems fitting to
call them the shark machines.
Shark machines available to students
There are 9 machines available to 15-213 students (the other 9 are allocated to 18-213). They run the same
Ubuntu operating system as the Andrew Linux cluster machines.
Students and teaching staff can log in to them using their Andrew
credentials. For example, if your Andrew ID is hbovik, then
you can log in to a random shark machine:
unix> ssh hbovik@shark.ics.cs.cmu.edu
or a specific machine:
unix> ssh hbovik@makoshark.ics.cs.cmu.edu
| makoshark.ics.cs.cmu.edu | milkshark.ics.cs.cmu.edu |
nurseshark.ics.cs.cmu.edu | pygmyshark.ics.cs.cmu.edu |
rivershark.ics.cs.cmu.edu |
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roughshark.ics.cs.cmu.edu | sandshark.ics.cs.cmu.edu |
sawshark.ics.cs.cmu.edu | tigershark.ics.cs.cmu.edu |
Frequently Asked Questions
Q: How do I get an account on a shark machine?
A: Anyone with a valid Andrew account can log in.
Help with the CMU computing environment
If you are new to CMU, here are some links to help you get started:
Technical specs
- 18 shark machines:
- Dell R410, 2x Intel E5520 CPUS, 2.67 GHz peak,
24 GB DRAM, 8 Nehalem cores, 160 GB SATA HDD
- Student machines:
64-bit Ubuntu 22.04.1 LTS (Linux kernel 5.15.0)
- Autograding servers:
Ubuntu Linux running Ubuntu virtual machines managed by Tashi
- Nehalem processor cores:
- 2-way hyperthreading
- L1 d-cache: 32 KB, 8-way associative (per core)
- L1 i-cache: 32 KB, 8-way associative (per core)
- L2 unified cache: 256 KB, 8-way associative (per core)
- L3 cache: 8 MB, 16-way associative (shared by all cores)
- 64-byte block size for L1, L2, and L3
- L1 d-TLB: 64 entries, 4-way associative (per core)
- L1 i-TLB: 128 entries, 4-way associative (per core)
- L2 unified TLB: 512 entries, 4-way associative
- DDR3 on-chip memory controller
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