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{\sc Agrawal, G., Sussman, A., and Salz, J.}
\newblock An integrated runtime and compile-time approach for parallelizing
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\newblock {\em {IEEE} Transaction on Parallel and Distributed Systems 6}, 7
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\bibitem{PENTIUM-MICRO-JOURNAL}
{\sc Alpert, D., and Avnon, D.}
\newblock Architecture of the {P}entium processor.
\newblock {\em {IEEE} Micro 13}, 3 (June 1993), 1--21.

\bibitem{POWER2-PROCESSOR-INPROCEEDINGS}
{\sc Barreh, J., Dhawan, S., Hicks, T., and Shippy, D.}
\newblock The {POWER2} processor.
\newblock In {\em Proceedings of COMPCON '94\/} (San Francisco, CA, March
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\bibitem{PPC601-MICRO-JOURNAL}
{\sc Becker, M.~C., Allen, M.~S., Moore, C.~R., Muhich, J.~S., and Tuttle,
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\newblock The {P}ower{PC} 601 processor.
\newblock {\em {IEEE} Micro 13}, 5 (October 1993), 54--68.

\bibitem{FAST-ASSEMBLY-ADDRESS-RELATIONS-TECHREPORT}
{\sc Dinda, P.~A., and O'Hallaron, D.~R.}
\newblock High throughput message assembly using compact address relations.
\newblock Tech. rep., Carnegie Mellon University, 1996.
\newblock To Appear.

\bibitem{AR-CACHING-LCR-INPROCEEDINGS}
{\sc Dinda, P.~A., and O'Hallaron, D.~R.}
\newblock The performance impact of address relation caching.
\newblock In {\em Proceedings of the Third International Workshop on Languages,
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\bibitem{DEC-ALPHA-21064-JOURNAL}
{\sc Dobberpuhl, D. i.~a.}
\newblock A 200-{MH}z 64-bit dual-issue {CMOS} microprocessor.
\newblock {\em Digital Technical Journal 4}, 4 (1992), 35--50.
\newblock ftp://ftp.digital.com/pub/Digital/info/DTJ/axp-cmos.txt.

\bibitem{DEC-3000-JOURNAL}
{\sc Dutton, T.~A., Eiref, D., Kurth, H.~R., Reisert, J.~J., and Stewart,
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\newblock The design of the {DEC} 3000 {AXP} systems, two high performance
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\newblock {\em Digital Technical Journal 4}, 4 (1992), 66--81.
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\bibitem{gupta94}
{\sc Gupta, S., Kaushik, S., Huang, C., and Sadayappan, P.}
\newblock On compiling array expressions for efficient execution on
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\newblock Tech. Rep. OSU-CISRC-4/94-TR19, Computer and Information Science
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\bibitem{hpf93}
{\sc {High Performance Fortran Forum}}.
\newblock {H}igh {P}erformance {F}ortran language specification, version 1.0.
\newblock Tech. Rep. CRPC-TR92225, Center for Research on Parallel Computation,
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\bibitem{HUFFMAN-CODES-JOURNAL}
{\sc Huffman, D.~A.}
\newblock A method for the construction of minimum-redundancy codes.
\newblock {\em Proceedings of the IRE 40}, 9 (September 1952), 1098--1101.

\bibitem{PARAGON-XPS-MANUAL}
{\sc Intel Corp.}
\newblock {\em Paragon X/PS Product Overview}, March 1991.

\bibitem{I860-PR-MANUAL}
{\sc Intel Corp.}
\newblock {\em {i}860 Microprocessor Family Programmer's Reference Manual},
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\bibitem{DATA-COMPRESSION-OVERVIEW-TECHREPORT}
{\sc Lelewer, D.~A., and Hirschberg, D.~S.}
\newblock Data compression.
\newblock Tech. Rep. 87-10, University of California -- Irvine, 1987.

\bibitem{ALPHA-MICRO-JOURNAL}
{\sc McLellan, E.}
\newblock The {A}lpha {AXP} architecture and 21064 processor.
\newblock {\em {IEEE} Micro 13}, 3 (June 1993), 36--47.

\bibitem{RS6000-ARCHITECTURE-JOURNAL}
{\sc Oehler, R., and Groves, R.}
\newblock {IBM} {RISC} system/6000 processor architecture.
\newblock {\em {IBM} Journal of Research and Development 34}, 1 (Jan 1990),
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\bibitem{PENTIUM-OVERVIEW-INPROCEEDINGS}
{\sc Saini, A.}
\newblock An overview of the {I}ntel {P}entium processor.
\newblock In {\em {COMPCON} Spring 1993 Digest of Papers\/} (San Francisco, CA,
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\bibitem{saltz91}
{\sc Saltz, J., , Petiton, S., Berryman, H., and Rifkin, A.}
\newblock Performance effects of irregular communication patterns on massively
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\newblock {\em Journal of Parallel and Distributed Computing 13\/} (1991),
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\bibitem{IBM-SP1}
{\sc Snir, M.}
\newblock {Scalable Parallel Computing - The IBM 9076 Scalable
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\newblock In {\em ACM Symposium on Parallel Algorithms and Architectures\/}
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\bibitem{GNECTAR-IFIP}
{\sc Steenkiste, P., Zill, B., Kung, H., Schlick, S., Hughes, J., Kowalski, B.,
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\newblock A host interface architecture for high-speed networks.
\newblock In {\em Proceedings of the 4th IFIP Conference on High Performance
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\bibitem{STEENKISTE-HOST-INTERFACE-DESIGN-JOURNAL}
{\sc Steenkiste, P.~A.}
\newblock A systematic approach to host interface design for high-speed
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\newblock {\em Computer 27}, 3 (March 1994), 47--57.

\bibitem{stichnoth93a}
{\sc Stichnoth, J.}
\newblock Efficient compilation of array statements for private memory
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\newblock Tech. Rep. CMU-CS-93-109, School of Computer Science, Carnegie Mellon
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\bibitem{stichnoth94}
{\sc Stichnoth, J., O'Hallaron, D., and Gross, T.}
\newblock Generating communication for array statements: Design,
  implementation, and evaluation.
\newblock {\em Journal of Parallel and Distributed Computing 21}, 1 (Apr.
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\bibitem{IRREGULAR-MALAGA}
{\sc Stichnoth, J., and T., G.}
\newblock A communication backend for parallel language compilers.
\newblock Proc. Fifth Workshop on Compilers for Parallel Languages, Malaga,
  Spain (Tech Report UMA-DAC-95/09), pages 65--77, 1995.

\bibitem{STRICKER-OPT-MEM-PERF-COMM-INPROCEEDINGS}
{\sc Stricker, T., and Gross, T.}
\newblock Optimizing memory system performance for communication in parallel
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\newblock In {\em Proc. 22nd Intl. Symp. on Computer Architecture\/}
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\bibitem{LZW-JOURNAL}
{\sc Welch, J.}
\newblock A technique for high performance data compression.
\newblock {\em IEEE Computer 17}, 6 (June 1984), 8--19.

\bibitem{POWER2-ARCH-INPROCEEDINGS}
{\sc White, S.~W.}
\newblock Power2: Architecture and performance.
\newblock In {\em Proceedings of COMPCON '94\/} (San Francisco, CA, March
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\bibitem{LZ-JOURNAL}
{\sc Ziv, J., and Lempel, A.}
\newblock A universal algorithm for sequential data compression.
\newblock {\em IEEE Transactions on Information Theory 23}, 3 (May 1977),
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