Seth Copen Goldstein Publications Listed by Year

@inproceedings{npgb16a,
  author = {Naz, Andre and Piranda, Beno{\^{\i}}t and Goldstein, Seth
     Copen and Bourgeois, Julien},
  title = {A Time Synchronization Protocol for Modular Robots},
  booktitle = {24th Euromicro International Conference on Parallel,
     Distributed, and Network-Based Processing, {PDP} 2016, Heraklion,
     Crete, Greece, February 17-19, 2016},
  pages = {109--118},
  year = {2016},
  url = {http://dx.doi.org/10.1109/PDP.2016.73},
  doi = {10.1109/PDP.2016.73},
}

@inproceedings{npgb16,
  author = {Naz, Andr{\'{e}} and Piranda, Beno{\^{\i}}t and Goldstein,
     Seth Copen and Bourgeois, Julien},
  title = {Approximate-Centroid Election in Large-Scale Distributed
     Embedded Systems},
  booktitle = {30th {IEEE} International Conference on Advanced
     Information Networking and Applications, {AINA} 2016,
     Crans-Montana, Switzerland, 23-25 March, 2016},
  pages = {548--556},
  year = {2016},
  url = {http://dx.doi.org/10.1109/AINA.2016.109},
  doi = {10.1109/AINA.2016.109},
}

@inproceedings{crb16,
  author = {Cruz, Fl{\'{a}}vio and Rocha, Ricardo and Goldstein, Seth
     Copen},
  title = {Declarative coordination of graph-based parallel programs},
  booktitle = {Proceedings of the 21st {ACM} {SIGPLAN} Symposium on
     Principles and Practice of Parallel Programming, PPoPP 2016,
     Barcelona, Spain, March 12-16, 2016},
  pages = {4:1--4:12},
  year = {2016},
  url = {http://doi.acm.org/10.1145/2851141.2851153},
  doi = {10.1145/2851141.2851153},
}

@article{bg15,
  author = {Bourgeois, Julien and Goldstein, Seth Copen},
  title = {Distributed Intelligent {MEMS:} Progresses and
     Perspectives},
  journal = {{IEEE} Systems Journal},
  volume = {9},
  number = {3},
  issn = {1932-8184},
  month = {Sep},
  keywords = {distributed programming;electronic engineering
     computing;knowledge based systems;mechanical engineering
     computing;micromechanical devices;communication;coordinated
     actuation;distributed computing;distributed intelligent MEMS
     systems;embedded intelligence;manufacturing
     scalability;microelectromechanical systems;mobility
     management;programming;Actuators;Hardware;Micromechanical
     devices;Network
     topology;Scalability;Sensors;Topology;Claytronics;Smart
     Blocks;Smart Surface;distributed computing;microelectromechanical
     systems (MEMS)},
  pages = {1057--1068},
  year = {2015},
  url = {http://dx.doi.org/10.1109/JSYST.2013.2281124},
  doi = {10.1109/JSYST.2013.2281124},
}

@inproceedings{npgb15,
  author = {Naz, Andre and Piranda, Beno{\^{\i}}t and Goldstein, Seth
     Copen and Bourgeois, Julien},
  title = {ABC-Center: Approximate-center election in modular robots},
  booktitle = {2015 {IEEE/RSJ} International Conference on Intelligent
     Robots and Systems, {IROS} 2015, Hamburg, Germany, September 28 -
     October 2, 2015},
  pages = {2951--2957},
  year = {2015},
  url = {http://dx.doi.org/10.1109/IROS.2015.7353784},
  doi = {10.1109/IROS.2015.7353784},
}

@article{lbmg15,
  author = {Lakhlef, Hicham and Bourgeois, Julien and Mabed, Hakim and
     Goldstein, Seth Copen},
  title = {Energy-aware parallel self-reconfiguration for chains
     microrobot networks},
  journal = {J. Parallel Distrib. Comput.},
  volume = {75},
  pages = {67--80},
  year = {2015},
  url = {http://dx.doi.org/10.1016/j.jpdc.2014.10.003},
  doi = {10.1016/j.jpdc.2014.10.003},
}

@inproceedings{crg15,
  author = {Cruz, Fl{\'{a}}vio and Rocha, Ricardo and Goldstein, Seth
     Copen},
  title = {Thread-Aware Logic Programming for Data-Driven Parallel
     Programs},
  booktitle = {Proceedings of the Technical Communications of the 31st
     International Conference on Logic Programming {(ICLP} 2015),
     Cork, Ireland, August 31 - September 4, 2015.},
  year = {2015},
  url = {http://ceur-ws.org/Vol-1433/tc_50.pdf},
}

@inproceedings{cruz-ppdp14,
  author = {Cruz, Fl{\'{a}}vio and Rocha, Ricardo and Goldstein, Seth
     Copen},
  title = {{Design and Implementation of a Multithreaded Virtual
     Machine for Executing Linear Logic Programs}},
  booktitle = {Proceedings of the International Symposium on
     Principles and Practice of Declarative Programming (PPDP 2014)},
  pages = {43--53},
  publisher = {ACM Press},
  editor = {O. Danvy},
  month = {Sep},
  url = {http://doi.acm.org/10.1145/2643135.2643150},
  doi = {10.1145/2643135.2643150},
  year = {2014},
  address = {Canterbury, UK},
}

@article{cruz-iclp14,
  author = {Cruz, Flavio and Rocha, Richard and Goldstein, Seth Copen
     and Pfenning, Frank},
  journal = {Journal of Theory and Practice of Logic Programming, 30th
     International Conference on Logic Programming (ICLP 2014),
     Special Issue},
  month = {Jul},
  pages = {493-507},
  title = {{A Linear Logic Programming Language for Concurrent
     Programming over Graph Structures}},
  year = {2014},
}

@article{kgr12a,
  author = {Karagozler, Mustafa Emre and Goldstein, Seth Copen and
     Ricketts, David S.},
  journal = {Circuits and Systems I: Regular Papers, IEEE Transactions
     on},
  title = {Analysis and Modeling of Capacitive Power Transfer in
     Microsystems},
  year = {2012},
  month = {Jul},
  volume = {59},
  number = {7},
  pages = {1557--1566},
  keywords = {Actuation, Adhesion,Power},
  doi = {10.1109/TCSI.2011.2177011},
  issn = {1549-8328},
}

@article{kgr12,
  author = {Karagozler, Mustafa Emre and Goldstein, Seth Copen and
     Ricketts, David S.},
  title = {Analysis and Modeling of Capacitive Power Transfer in
     Microsystems},
  journal = {IEEE Trans. on Circuits and Systems},
  volume = {59-I},
  number = {7},
  year = {2012},
  pages = {1557-1566},
}

@inproceedings{bg11,
  author = {Bourgeois, Julien and Goldstein, Seth Copen},
  title = {Distributed Intelligent {MEMS}: Progresses and
     Perspectives},
  booktitle = {ICT Innovations 2011},
  pages = {15--25},
  series = {Advances in Intelligent and Soft Computing},
  volume = {150},
  isbn = {978-3-642-28663-6},
  editor = {Kocarev, Ljupco},
  address = {Ohrid, Macedonia},
  publisher = {Springer Berlin / Heidelberg},
  year = {2012},
  note = {Keynote talk at the ICT Innovations 2011 conference},
  keywords = {Claytronics},
}

@inproceedings{ktgr11,
  author = {Karagozler, Mustafa Emre and Thaker, A. and Goldstein,
     Seth Copen and Ricketts, David S.},
  booktitle = {Circuits and Systems (ISCAS), 2011 IEEE International
     Symposium on},
  title = {Electrostatic actuation and control of micro robots using a
     post-processed high-voltage SOI CMOS chip},
  year = {2011},
  month = {May},
  pages = {2509--2512},
  keywords = {Si backside carrier substrate;electrostatic actuation
     electrodes;energy efficient control;low power digital
     design;micro robots;parasitic FET gates;post-processed
     high-voltage SOI CMOS chip;power conversion circuit;CMOS
     integrated circuits;electrodes;electrostatic
     actuators;microrobots;silicon-on-insulator;},
  keywords = {Si backside carrier substrate;electrostatic actuation
     electrodes;energy efficient control;low power digital
     design;micro robots;parasitic FET gates;post-processed
     high-voltage SOI CMOS chip;power conversion circuit;CMOS
     integrated circuits;electrodes;electrostatic
     actuators;microrobots;silicon-on-insulator;},
  doi = {10.1109/ISCAS.2011.5938114},
  issn = {0271-4302},
}

@inproceedings{kag11,
  author = {Kirby, Brian T. and Ashley-Rollman, Michael and Goldstein,
     Seth Copen},
  title = {Blinky blocks: a physical ensemble programming platform},
  booktitle = {CHI '11 Extended Abstracts on Human Factors in
     Computing Systems},
  series = {CHI EA '11},
  year = {2011},
  isbn = {978-1-4503-0268-5},
  pages = {1111--1116},
  doi = {10.1145/1979742.1979712},
  publisher = {ACM},
  address = {New York, NY, USA},
  keywords = {development tools, programming environments, robots,
     tangible UI},
  keywords = {development tools, programming environments, robots,
     tangible UI},
}

@article{DBLP:journals/puc/WellerGG11,
  author = {Weller, Michael Philetus and Gross, Mark D. and Goldstein,
     Seth Copen},
  title = {Hyperform specification: designing and interacting with
     self-reconfiguring materials},
  journal = {Personal and Ubiquitous Computing},
  volume = {15},
  number = {2},
  pages = {133--149},
  year = {2011},
  url = {http://dx.doi.org/10.1007/s00779-010-0315-7},
  doi = {10.1007/s00779-010-0315-7},
}

@inproceedings{karagozler-iros09,
  author = {Karagozler, Mustafa Emre and Goldstein, Seth Copen and
     Reid, James Robert},
  title = {Stress-Driven MEMS Assembly + Electrostatic Forces = 1mm
     Diameter Robot},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems ({IROS '09})},
  venue = {IEEE/RSJ International Conference on Intelligent Robots and
     Systems (IROS)},
  see = {karagozler-iros09},
  year = {2009},
  month = {Oct},
  abstract = {As the size of the modules in a self-reconfiguring
     modular robotic system shrinks and the number of modules
     increases, the flexibility of the system as a whole increases. In
     this paper, we describe the manufacturing methods and mechanisms
     for a 1 millimeter diameter module which can be manufactured en
     masse. The module is the first step towards realizing the basic
     unit of claytronics, a modular robotic system designed to scale
     to millions of units.},
  keywords = {Actuation, Adhesion, Robot Fabrication},
  url = {http://www.cs.cmu.edu/~claytronics/papers/karagozler-iros09.pdf},
}

@inproceedings{ashley-rollman-iclp09,
  author = {Ashley-Rollman, Michael P. and Lee, Peter and Goldstein,
     Seth Copen and Pillai, Padmanabhan and Campbell, Jason D.},
  booktitle = {Proceedings of the International Conference on Logic
     Programming (ICLP '09)},
  title = {A Language for Large Ensembles of Independently Executing
     Nodes},
  year = {2009},
  month = {Jul},
  keywords = {Distributed Systems, Meld, Programming Languages},
  url = {http://www.cs.cmu.edu/~claytronics/papers/ashley-rollman-iclp09.pdf},
  abstract = {We address how to write programs for distributed
     computing systems in which the network topology can change
     dynamically. Examples of such systems, which we call {\em
     ensembles}, include programmable sensor networks (where the
     network topology can change due to failures in the nodes or
     links) and modular robotics systems (whose physical configuration
     can be rearranged under program control). We extend Meld, a logic
     programming language that allows an ensemble to be viewed as a
     single computing system. In addition to proving some key
     properties of the language, we have also implemented a complete
     compiler for Meld. It generates code for TinyOS and for a
     Claytronics simulator. We have successfully written correct,
     efficient, and complex programs for ensembles containing over one
     million nodes.},
  booktitle = {Proceedings of the International Conference on Logic
     Programming (ICLP '09)},
}

@article{goldstein09,
  author = {Goldstein, Seth Copen and Mowry, Todd C. and Campbell,
     Jason D. and Ashley-Rollman, Michael P. and De~Rosa, Michael and
     Funiak, Stanislav and Hoburg, James F. and Karagozler, Mustafa
     Emre and Kirby, Brian and Lee, Peter and Pillai, Padmanabhan and
     Reid, J. Robert and Stancil, Daniel D. and Weller, Michael
     Philetus},
  title = {Beyond Audio and Video: Using Claytronics to Enable Pario},
  journal = {AI Magazine},
  year = {2009},
  volume = {30},
  number = {2},
  month = {Jul},
  keywords = {Claytronics},
  abstract = {In this article, we describe the hardware and software
     challenges involved in realizing Claytronics, a form of
     programmable matter made out of very large numbers-potentially
     millions-of submillimeter sized spherical robots. The goal of the
     claytronics project is to create ensembles of cooperating
     submillimeter robots, which work together to form dynamic 3D
     physical objects. For example, claytronics might be used in
     telepresense to mimic, with high-fidelity and in 3-dimensional
     solid form, the look, feel, and motion of the person at the other
     end of the telephone call. To achieve this long-range vision we
     are investigating hardware mechanisms for constructing
     submillimeter robots, which can be manufactured en masse using
     photolithography. We also propose the creation of a new media
     type, which we call pario. The idea behind pario is to render
     arbitrary moving, physical 3-dimensional objects that you can
     see, touch, and even hold in your hands. In parallel with our
     hardware effort, we are developing novel distributed programming
     languages and algorithms to control the ensembles, LDP and Meld.
     Pario may fundamentally change how we communicate with others and
     interact with the world around us. Our research results to date
     suggest that there is a viable path to implementing both the
     hardware and software necessary for claytronics, which is a form
     of programmable matter that can be used to implement pario. While
     we have made significant progress, there is still much research
     ahead in order to turn this vision into reality.},
}

@article{cannon-tranpe09,
  author = {Cannon, Benjamin L. and Hoburg, James F. and Stancil,
     Daniel D. and Goldstein, Seth Copen},
  title = {Magnetic resonant coupling as a potential means for
     wireless power transfer to multiple small receivers},
  year = {2009},
  url = {http://www.cs.cmu.edu/~claytronics/papers/cannon-tranpe09.pdf},
  month = {Jul},
  volume = {24},
  number = {7},
  journal = {IEEE Transactions on Power Electronics},
  keywords = {Power},
  abstract = {Wireless power transfer via magnetic resonant coupling
     is experimentally demonstrated in a system with a large source
     coil and either one or two small receivers. Resonance between
     source and load coils is achieved with lumped capacitors
     terminating the coils. A circuit model is developed to describe
     the system with a single receiver, and extended to describe the
     system with two receivers. With parameter values chosen to obtain
     good fits, the circuit models yield transfer frequency responses
     that are in good agreement with experimental measurements over a
     range of frequencies that span the resonance. Resonant frequency
     splitting is observed experimentally and described theoretically
     for the multiple receiver system. In the single receiver system
     at resonance, more than 50\% of the power that is supplied by the
     actual source is delivered to the load. In a multiple receiver
     system, a means for tracking frequency shifts and continuously
     retuning the lumped capacitances that terminate each receiver
     coil so as to maximize efficiency is a key issue for future
     work.},
}

@article{funiak-ijrr09,
  author = {Funiak, Stanislav and Pillai, Padmanabhan and
     Ashley-Rollman, Michael P. and Campbell, Jason D. and Goldstein,
     Seth Copen},
  title = {Distributed Localization of Modular Robot Ensembles},
  journal = {International Journal of Robotics Research},
  year = {2009},
  abstract = {Internal localization, the problem of estimating
     relative pose for each module of a modular robot, is a
     prerequisite for many shape control, locomotion, and actuation
     algorithms. In this paper, we propose a robust hierarchical
     approach that uses normalized cut to identify dense sub-regions
     with small mutual localization error, then progressively merges
     those sub-regions to localize the entire ensemble. Our method
     works well in both two and three dimensions, and requires neither
     exact measurements nor rigid inter-module connectors. Most of the
     computations in our method can be distributed effectively. The
     result is a robust algorithm that scales to large ensembles. We
     evaluate our algorithm in two- and three-dimensional simulations
     of scenarios with up to 10,000 modules.},
  volume = {28},
  number = {8},
  pages = {946--61},
}

@inproceedings{koes-scopes09,
  author = {Koes, David Ryan and Goldstein, Seth Copen},
  title = {Register allocation deconstructed},
  booktitle = {SCOPES '09: Proceedings of th 12th International
     Workshop on Software and Compilers for Embedded Systems},
  year = {2009},
  isbn = {978-1-60558-696-0},
  pages = {21--30},
  abstract = {Register allocation is a fundamental part of any
     optimizing compiler. Effectively managing the limited register
     resources of the constrained architectures commonly found in
     embedded systems is essential in order to maximize code quality.
     In this paper we deconstruct the register allocation problem into
     distinct components: coalescing, spilling, move insertion, and
     assignment. Using an optimal register allocation framework, we
     empirically evaluate the importance of each of the components,
     the impact of component integration, and the effectiveness of
     existing heuristics. We evaluate code quality both in terms of
     code performance and code size and consider four distinct
     instruction set architectures: ARM, Thumb, x86, and x86-64. The
     results of our investigation reveal general principles for
     register allocation design.},
}

@inproceedings{venkataramani-codes08,
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM/IFIP International Conference on
     Hardware/Software Codesign and System Synthesis {(CODES-ISSS)}},
  year = {2008},
  address = {Atlanta, GE},
  month = {Oct},
  keywords = {Asychronous Circuits, CAD, Global Critical Path},
  title = {Slack Analysis in the System Design Loop},
  talk = {http://www.cs.cmu.edu/~seth/papers/talk-venkataramani-codes08.pdf},
  pages = {231--236},
}

@inproceedings{dewey-iros08,
  author = {Dewey, Daniel and Srinivasa, Siddhartha S. and
     Ashley-Rollman, Michael P. and De~Rosa, Michael and Pillai,
     Padmanabhan and Mowry, Todd C. and Campbell, Jason D. and
     Goldstein, Seth Copen},
  title = {Generalizing Metamodules to Simplify Planning in Modular
     Robotic Systems},
  booktitle = {Proceedings of IEEE/RSJ 2008 International Conference
     on Intelligent Robots and Systems {IROS '08}},
  year = {2008},
  address = {Nice, France},
  month = {Sep},
  abstract = {In this paper we develop a theory of metamodules and an
     associated distributed asynchronous planner which generalizes
     previous work on metamodules for lattice-based modular robotic
     systems. All extant modular robotic systems have some form of
     non-holonomic motion constraints. This has prompted many
     researchers to look to metamodules, i.e., groups of modules that
     act as a unit, as a way to reduce motion constraints and the
     complexity of planning. However, previous metamodule designs have
     been specific to a particular modular robot. 
By analyzing the
     constraints found in modular robotic systems we develop a
     holonomic metamodule which has two important properties: (1) it
     can be used as the basic unit of an efficient planner and (2) it
     can be instantiated by a wide variety of different underlying
     modular robots, e.g., modular robot arms, expanding cubes,
     hex-packed spheres, etc. Using a series of transformations we
     show that our practical metamodule system has a provably complete
     planner. Finally, our approach allows the task of shape
     transformation to be separated into a planning task and a
     resource allocation task. We implement our planner for two
     different metamodule systems and show that the time to completion
     scales linearly with the diameter of the ensemble.},
  url = {http://www.cs.cmu.edu/~claytronics/papers/dewey-iros08.pdf},
  keywords = {Meld, Planning, Multi-Robot Formations, Controlling
     Ensembles, Robotics},
}

@inproceedings{funiak-rss08,
  author = {Funiak, Stanislav and Pillai, Padmanabhan and
     Ashley-Rollman, Michael P. and Campbell, Jason D. and Goldstein,
     Seth Copen},
  title = {Distributed Localization of Modular Robot Ensembles},
  booktitle = {Proceedings of Robotics: Science and Systems},
  year = {2008},
  month = {Jun},
  abstract = {Internal localization, the problem of estimating
     relative pose for each module (part) of a modular robot is a
     prerequisite for many shape control, locomotion, and actuation
     algorithms. In this paper, we propose a robust hierarchical
     approach that uses normalized cut to identify dense subregions
     with small mutual localization error, then progressively merges
     those subregions to localize the entire ensemble. Our method
     works well in both 2D and 3D, and requires neither exact
     measurements nor rigid inter-module connectors. Most of the
     computations in our method can be effectively distributed. The
     result is a robust algorithm that scales to large,
     non-homogeneous ensembles. We evaluate our algorithm in accurate
     2D and 3D simulations of scenarios with up to 10,000 modules.},
  keywords = {Distributed Systems, Localization, Meld},
  url = {http://www.cs.cmu.edu/~claytronics/papers/funiak-rss2008.pdf},
  see = {funiak-ijrr09},
}

@article{mderosa-ijrr-2008,
  author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
     and Campbell, Jason D. and Pillai, Padmanabhan},
  journal = {International Journal of Robotics Research},
  keywords = {Debugging Distributed Systems},
  month = {Mar},
  note = {Special Issue on Modular Robotics},
  url = {http://www.cs.cmu.edu/~claytronics/papers/mderosa-ijrr-2008.pdf},
  venue = {International Journal of Robotics Research},
  number = {3},
  title = {Distributed Watchpoints: Debugging Large Modular Robotic
     Systems},
  abstract = {Distributed systems frequently exhibit properties of
     interest which span multiple entities. These properties cannot
     easily be detected from any single entity, but can be readily be
     detected by combining the knowledge of multiple entities. Testing
     for distributed properties is especially important in debugging
     or verifying software for modular robots. We have developed a
     technique we call distributed watchpoint triggers which can
     efficiently recognize distributed conditions. Our watchpoint
     description language can handle a variety of temporal, spatial,
     and logical properties spanning multiple robots. This paper
     presents the specification language, describes the distributed
     online mechanism for detecting distributed conditions in a
     running system, and evaluates the performance of our
     implementation.},
  volume = {27},
  also = {Distributed Watchpoints: Debugging Large Multi-Robot
     Systems, (ICRA07)},
  year = {2008},
}

@techreport{dewey08,
  author = {Dewey, Daniel and Srinivasa, Siddhartha and
     Ashley-Rollman, Michael and De Rosa, Michael and Pillai,
     Padmanabhan and Mowry, Todd and Campbell, Jason and Goldstein,
     Seth Copen},
  title = {Generalizing metamodules to simplify planning in modular
     robotic systems},
  institution = {Carnegie Mellon University},
  year = {2008},
  number = {CMU-CS-08-139},
}

@inproceedings{venkataramani-async08,
  author = {Venkataramani, Girish and Chelcea, Tiberiu and Goldstein,
     Seth Copen},
  title = {Heterogeneous Latch-Based Asynchronous Pipelines},
  journal = {Asynchronous Circuits and Systems, International
     Symposium on},
  year = {2008},
  issn = {1522-8681},
  pages = {83--92},
  keywords = {Asychronous Circuits},
  doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2008.21},
  publisher = {IEEE Computer Society},
  address = {Los Alamitos, CA, USA},
  abstract = {We present a technique to automatically synthesize
     heterogeneous asynchronous pipelines by combining two different
     latching styles: normally open D-latches for high performance and
     self-resetting D-latches for low power. Theformer is fast but
     results in high power consumption due to data glitches that leak
     through the latch when it is open. The latter is normally closed
     and is opened just before data stabilizes. Thus, it is more
     power-efficient but slower than normally open D-latches. We
     propose a module selection optimization that assigns each
     pipeline stage to one of these two latching styles. This is
     performed by an automated algorithm that uses two types of
     heuristics: (1) it uses the Global Critical Path (GCP), to assign
     D-latches to stages that are sequentially critical, and (2) it
     estimates potential datapath glitching to make SR-latch
     assignment decisions. The algorithm has quadratic-time complexity
     and experiments that apply the algorithm on several media
     processing kernels indicate that, on average, the heterogeneous
     pipelining algorithm achieves higher performance and is more
     energy efficient than either the homogeneous D-latch or SR-latch
     pipeline styles.},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-async08.pdf},
}

@inproceedings{koes-cgo08,
  author = {Koes, David Ryan and Goldstein, Seth Copen},
  title = {Near-Optimal Instruction Selection on {DAG}s},
  booktitle = {Proceedings of the International Symposium on Code
     Generation and Optimization {(CGO'08)}},
  year = {2008},
  keywords = {Compilers:Instruction Selection},
  abstract = {Instruction selection is a key component of code
     generation. High quality instruction selection is of particular
     importance in the embedded space where complex instruction sets
     are common and code size is a prime concern. Although instruction
     selection on tree expressions is a well understood and easily
     solved problem, instruction selection on directed acyclic graphs
     is NP-complete. In this paper we present NOLTIS, a near-optimal,
     linear time instruction selection algorithm for DAG expressions.
     NOLTIS is easy to implement, fast, and effective with a
     demonstrated average code size improvement of 5.1\% compared to
     the traditional tree decomposition and tiling approach.},
  publisher = {IEEE Computer Society},
  url = {http://www.cs.cmu.edu/~seth/papers/koes-cgo08.pdf},
  address = {Washington, DC, USA},
}

@inproceedings{derosa-icra08,
  author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
     and Campbell, Jason D. and Pillai, Padmanabhan},
  booktitle = {Proceedings of the IEEE International Conference on
     Robotics and Automation {ICRA '08}},
  venue = {IEEE International Conference on Robotics and Automation
     (ICRA)},
  keywords = {Claytronics, Modular Robotics, Programming, LDP},
  title = {Programming Modular Robots with Locally Distributed
     Predicates},
  year = {2008},
  abstract = {We present a high-level language for programming modular
     robotic systems, based on locally distributed predicates (LDP),
     which are distributed conditions that hold for a connected
     subensemble of the robotic system. An LDP program is a collection
     of LDPs with associated actions which are triggered on any
     subensemble that matches the predicate. The result is a reactive
     programming language which efficiently and concisely supports
     ensemble-level programming. We demonstrate the utility of LDP by
     implementing three common, but diverse, modular robotic tasks.},
  url = {http://www.cs.cmu.edu/~claytronics/papers/derosa-icra08.pdf},
}

@techreport{cannon08,
  author = {Cannon, Benjamin L. and Hoburg, James F. and Stancil,
     Daniel D. and Goldstein, Seth Copen},
  title = {Magnetic Resonant Coupling as a Potential Means for
     Wireless Power Transfer to Multiple Small Receivers},
  institution = {Carnegie Mellon University},
  year = {2008},
  number = {CMU-CS-08-167},
  month = {Dec},
}

@inproceedings{bkirby-iros07,
  author = {Kirby, Brian and Aksak, Burak and Goldstein, Seth Copen
     and Hoburg, James F. and Mowry, Todd C. and Pillai, Padmanabhan},
  title = {A Modular Robotic System Using Magnetic Force Effectors},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems ({IROS '07})},
  year = {2007},
  month = {Oct},
  abstract = {One of the primary impediments to building ensembles
     with many modular robots is the complexity and number of
     mechanical mechanisms used to construct the individual modules.
     As part of the Claytronics project---which aims to build very
     large ensembles of modular robots---we investigate how to
     simplify each module by eliminating moving parts and reducing the
     number of mechanical mechanisms on each robot by using
     force-at-a-distance actuators. Additionally, we are also
     investigating the feasibility of using these unary actuators to
     improve docking performance, implement intermodule adhesion,
     power transfer, communication, and sensing.},
  keywords = {Claytronics, Actuation, Adhesion},
  url = {http://www.cs.cmu.edu/~claytronics/papers/bkirby-iros07.pdf},
}

@inproceedings{ravichandran-iros07,
  author = {Ravichandran, Ramprasad and Gordon, Geoffrey and
     Goldstein, Seth Copen},
  title = {A Scalable Distributed Algorithm for Shape Transformation
     in Multi-Robot Systems},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems {IROS '07}},
  year = {2007},
  month = {Oct},
  keywords = {Claytronics, Multi-Robot Formations},
  abstract = {Distributed reconfiguration is an important problem in
     multi-robot systems such as mobile sensor nets and metamorphic
     robot systems. In this work, we present a scalable distributed
     reconfiguration algorithm, Hierarchical Median Decomposition, to
     achieve arbitrary target configurations. Our algorithm is built
     on top of a novel distributed median consensus estimator. The
     algorithms presented are fully distributed and do not require
     global communication. We show results from simulations in an open
     source multi-robot simulator.},
  url = {http://www.cs.cmu.edu/~claytronics/papers/ravichandran-iros07.pdf},
}

@inproceedings{ashley-rollman-derosa-iros07wksp,
  author = {Ashley-Rollman, Michael P. and De~Rosa, Michael and
     Srinivasa, Siddhartha S. and Pillai, Padmanabhan and Goldstein,
     Seth Copen and Campbell, Jason D.},
  title = {Declarative Programming for Modular Robots},
  booktitle = {Workshop on Self-Reconfigurable Robots/Systems and
     Applications at {IROS '07}},
  year = {2007},
  month = {Oct},
  keywords = {Claytronics, Programming Models, Planning, LDP, Meld},
  abstract = {Because of the timing, complexity, and asynchronicity
     challenges common in modular robot software we have recently
     begun to explore new programming models for modular robot
     ensembles. In this paper we apply two of those models to a
     metamodule-based shape planning algorithm and comment on the
     differences between the two approaches. Our results suggest that
     declarative programming can provide several advantages over more
     traditional imperative approaches, and that the differences
     between declarative programming styles can themselves contribute
     leverage to different parts of the problem domain.},
  url = {http://www.cs.cmu.edu/~claytronics/papers/ashley-rollman-derosa-iros07wksp.pdf},
}

@inproceedings{karagozler-iros07,
  author = {Karagozler, Mustafa Emre and Campbell, Jason D. and
     Fedder, Gary K. and Goldstein, Seth Copen and Weller, Michael
     Philetus and Yoon, Byung W.},
  title = {Electrostatic Latching for Inter-module Adhesion, Power
     Transfer, and Communication in Modular Robots},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems ({IROS '07})},
  year = {2007},
  month = {Oct},
  abstract = {A simple and robust inter-module latch is possibly the
     most important component of a modular robotic system. This paper
     describes a latch based on capacitive coupling which not only
     provides significant adhesion forces, but can also be used for
     inter-module power transmission and communication. The key
     insight that enables electrostatic adhesion to be effective at
     the macroscale is to combine flexible electrodes with a geometery
     that uses shear forces to provide adhesion. To measure the
     effectiveness of our latch we incorporated it into a 28cm x 28cm
     x 28cm modular robot. The result is a latch which requires almost
     zero static power and yet can hold over 0.6N/cm^2 of latch
     area.},
  keywords = {Actuation, Adhesion, Claytronics},
  url = {http://www.cs.cmu.edu/~claytronics/papers/karagozler-iros07.pdf},
}

@inproceedings{funiak-iros07,
  author = {Funiak, Stanislav and Pillai, Padmanabhan and Campbell,
     Jason D. and Goldstein, Seth Copen},
  title = {Internal Localization of Modular Robot Ensembles},
  booktitle = {Workshop on Self-Reconfiguring Modular Robotics at the
     IEEE International Conference on Intelligent Robots and Systems
     (IROS) '07},
  year = {2007},
  month = {Oct},
  abstract = {The determination of the relative position and pose of
     every robot in a modular robotic ensemble is a necessary
     preliminary step for most modular robotic tasks. Localization is
     particularly important when the modules make local noisy
     observations and are not significantly constrained by inter-robot
     latches. In this paper, we propose a robust hierarchical approach
     to the {\em internal localization} problem that uses normalized
     cut to identify subproblems with small localization error. A key
     component of our solution is a simple method to reduce the cost
     of normalized cut computations. The result is a robust algorithm
     that scales to large, non-homogeneous ensembles. We evaluate our
     algorithm in simulation on ensembles of up to 10,000 modules,
     demonstrating substantial improvements over prior work.},
  keywords = {Claytronics, Probabilistic Inference, Sensing,
     Localization, Distributed Algorithms},
  url = {http://www.cs.cmu.edu/~claytronics/papers/funiak-iros07.pdf},
}

@inproceedings{ashley-rollman-iros07,
  author = {Ashley-Rollman, Michael P. and Goldstein, Seth Copen and
     Lee, Peter and Mowry, Todd C. and Pillai, Padmanabhan},
  title = {Meld: A Declarative Approach to Programming Ensembles},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems ({IROS '07})},
  year = {2007},
  month = {Oct},
  keywords = {Claytronics, Programming Languages, Meld},
  abstract = {This paper presents Meld, a programming language for
     modular robots, i.e., for independently executing robots where
     inter-robot communication is limited to immediate neighbors. Meld
     is a declarative language, based on P2, a logic-programming
     language originally designed for programming overlay networks. By
     using logic programming, the code for an ensemble of robots can
     be written from a global perspective, as opposed to a large
     collection of independent robot views. This greatly simplifies
     the thought process needed for programming large ensembles.
     Initial experience shows that this also leads to a considerable
     reduction in code size and complexity. An initial implementation
     of Meld has been completed and has been used to demonstrate its
     effectiveness in the Claytronics simulator. Early results
     indicate that Meld programs are considerably more concise (more
     than 20x shorter) than programs written in C++, while running
     nearly as efficiently.},
  url = {http://www.cs.cmu.edu/~claytronics/papers/ashley-rollman-iros07.pdf},
}

@inproceedings{weller-iros07,
  author = {Weller, Michael Philetus and Karagozler, Mustafa Emre and
     Kirby, Brian and Campbell, Jason D. and Goldstein, Seth Copen},
  title = {Movement Primitives for an Orthogonal Prismatic
     Closed-Lattice-Constrained Self-Reconfiguring Module},
  booktitle = {Workshop on Self-Reconfiguring Modular Robotics at the
     IEEE International Conference on Intelligent Robots and Systems
     (IROS) '07},
  year = {2007},
  month = {Oct},
  keywords = {Claytronics, Adhesion, Robotics, Planning},
  abstract = {We describe a new set of prismatic movement primitives
     for cubic modular robots. Our approach appears more practical
     than previous metamodule-based approaches. We also describe
     recent hardware developments in our cubic robot modules that have
     sufficient stiffness and actuator strength so that when they work
     together they can realize, in earth's gravity, all of the motion
     primitives we describe here.},
  url = {http://www.cs.cmu.edu/~claytronics/papers/weller-iros07.pdf},
}

@inproceedings{dac07-gcp,
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  title = {Global Critical Path: A Tool for System-Level Timing
     Analysis},
  booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
     Conference},
  year = {2007},
  month = {Jun},
  address = {San Diego, CA},
  pages = {783--786},
  abstract = {An effective method for focusing optimization effort on
     the most important parts of a design is to examine those elements
     on the critical path. Traditionally, the critical path is defined
     at the RTL level, as the longest path in the combinational logic
     between clocked reisters. In this paper, we present a
     system-level timing analysis technique to define the concept of a
     Global Critical Path (GCP), for predicting system-level
     performance. We show how the GCP can be used as a theoretical and
     practical tool for understanding, summarizing and optimizing the
     behavior of highly concurrent self-timed circuits. We formally
     define the GCP and show how it can be constructed using a
     discrete event model and hardware profiling techniques. The GCP
     provides valuable insight into the control-path behavior of
     circuits and in finding system-level bottlenecks. We have
     incorporated the GCP construction and analysis framework into a
     high-level synthesis and simulation toolchain, thus enabling
     complete automation in modeling, analysis and optimization.},
  url = {http://www.cs.cmu.edu/~seth/papers/dac07-gcp.pdf},
  keywords = {Asychronous Circuits, CAD, Global Critical Path, System
     modeling, Hardware profiling},
}

@inproceedings{dac07-sr,
  author = {Chelcea, Tiberiu and Venkataramani, Girish and Goldstein,
     Seth Copen},
  title = {Self-Resetting Latches for Asynchronous Micro-Pipelines},
  booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
     Conference},
  year = {2007},
  month = {Jun},
  address = {San Diego, CA},
  pages = {986--989},
  keywords = {Asychronous Circuits},
  abstract = {Asynchronous circuits are increasingly attractive as low
     power or high-performance replacements to synchronous designs. A
     key part of these circuits are asynchronous micropipelines;
     unfortunatelly, the existing micropipeline styles either improve
     performance or decrease power consumption, but not both. Very
     often, the pipeline register plays a crucial role in these cost
     metrics. In this paper we introduce a new register design, called
     self-resetting latches, for asynchronous micropipelines which
     bridges the gap between fast, but power hungry, latch-based
     designs and slow, but low power, flip-flop designs. The
     energy-delay metric for large asynchronous systems implemented
     with self-resetting latches is, on average, 41\% better than
     latch-based designs and 15\% better than flip-flop designs.},
  url = {http://www.cs.cmu.edu/~seth/papers/dac07-sr.pdf},
}

@inproceedings{derosa-icra07,
  abstract = {Tightly-coupled multi-agent systems such as modular
     robots frequently exhibit properties of interest that span
     multiple modules. These properties cannot easily be detected from
     any single module, though they might readily be detected by
     combining the knowledge of multiple modules. Testing for
     distributed conditions is especially important in debugging or
     verifying the correctness of software for modular robots. We have
     developed a technique we call distributed watchpoint triggers
     which can efficiently recognize such distributed conditions. Our
     watchpoint description language can handle a variety of temporal,
     spatial, and logical properties spanning multiple robots. This
     paper presents that language, describes our fully-distributed,
     online mechanism for detecting distributed conditions in a
     running system, and evaluates the performance of our
     implementation. We found that the performance of the system is
     highly dependent on the program being debugged, scales linearly
     with ensemble size, and is small enough to make the system
     practical in all but the worst case scenarios.},
  author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
     and Campbell, Jason D. and Pillai, Padmanabhan and Mowry, Todd
     C.},
  booktitle = {Proceedings of the IEEE International Conference on
     Robotics and Automation {ICRA '07}},
  venue = {IEEE International Conference on Robotics and Automation
     (ICRA)},
  title = {Distributed Watchpoints: Debugging Large Multi-Robot
     Systems},
  see = {mderosa-ijrr-2008},
  year = {2007},
  month = {Apr},
  keywords = {Debugging, Distributed Algorithms},
  url = {http://www.cs.cmu.edu/~claytronics/papers/derosa-icra07.pdf},
}

@inproceedings{chelcea-async07,
  author = {Chelcea, Tiberiu and Venkataramani, Girish and Goldstein,
     Seth Copen},
  title = {Area Optimizations for Dual-Rail Circuits Using
     Relative-Timing Analysis},
  booktitle = {Proceedings of the 13th IEEE International Symposium on
     Asynchronous Circuits and Systems},
  year = {2007},
  address = {Berkeley, CA},
  month = {Mar},
  pages = {117--128},
  abstract = {Future deep sub-micron technologies will be
     characterized by large parametric variations, which could make
     asynchronous design an attractive solution for use on large
     scale. However, the investment in asynchronous CAD tools does not
     approach that in synchronous ones. Even when asynchronous tools
     leverage existing synchronous toolflows, they introduce large
     area and speed overheads. This paper proposes several heuristic
     and optimal algorithms, based on timing interval analysis, for
     improving existing asynchronous CAD solutions by optimizing area.
     The optimized circuits are 2.4 times smaller for an optimal
     algorithm and 1.8 times smaller for a heuristic one than the
     existing solutions. The optimized circuits are also shown to be
     resilient to large parametric variations, yielding better
     average-case latencies than their synchronous counterparts.},
  url = {http://www.cs.cmu.edu/~seth/papers/chelcea-async07.pdf},
  keywords = {Asychronous Circuits, CAD},
}

@inproceedings{venkataramani-iccad07,
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  title = {Operation Chaining Asynchronous Pipelined Circuits},
  booktitle = {ICCAD},
  abstract = {We define operation chaining (op-chaining) as an
     optimization problem to determine the optimal pipeline depth for
     balancing performance against energy demands in pipelined
     asynchronous designs. Since there are no clock period
     requirements, asynchronous pipeline stages can have non-uniform
     latencies. We exploit this fact to coalesce several stages
     together thereby saving power and area due to the elimination of
     control-path resources from the pipeline. The trade-off is
     potentially reduced pipeline parallelism. 
In this paper, we
     formally define this optimization as a graph covering problem,
     which finds sub-graphs that will be synthesized as an opchained
     pipeline stage. We then define the solution space for provably
     correct solutions and present an algorithm to efficiently search
     this space. The search technique partitions the graph based on
     post-dominator relationships to find sub-graphs that are
     potential op-chain candidates. We use knowledge of the Global
     Critical Path (GCP) [13] to evaluate the performance impact of
     accepting a candidate sub-graph and formulate a heuristic cost
     function to model this trade-off. The algorithm has a
     quadratic-time complexity in the size of the dataflow graph. We
     have implemented this algorithm within an automated asynchronous
     synthesis toolchain [12]. Experimental evidence from applying the
     algorithm on several media processing kernels reveals that the
     average energy-delay and energy-delay-area products improve by
     about 1.4x and 1.8x respectively, with a maximum improvement of
     5x and 18x.},
  month = {Nov},
  year = {2007},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iccad07.pdf},
  keywords = {Asychronous Circuits, CAD, Global Critical Path},
}

@inproceedings{goldstein-waci06,
  author = {Goldstein, Seth Copen},
  title = {Brain in a Bottle},
  booktitle = {Wild and Crazy Ideas Session of ASPLOS},
  year = {2006},
  month = {Oct},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-waci06.pdf},
  keywords = {Brain, Parallel Computing, Self-Assembly},
}

@inproceedings{bhat06,
  author = {Bhat, Preethi Srinivas and Kuffner, James and Goldstein,
     Seth Copen and Srinivasa, Siddhartha},
  title = {Hierarchical Motion Planning for Self-reconfigurable
     Modular Robots},
  booktitle = {2006 IEEE/RSJ International Confernce on Intelligent
     Robots and Systems (IROS)},
  year = {2006},
  month = {Oct},
  keywords = {Claytronics, Planning, Modular Robotics},
  url = {http://www.cs.cmu.edu/~seth/papers/bhat06.pdf},
}

@inproceedings{mahim-asplos06,
  title = {Tartan: Evaluating Spatial Computation for Whole Program
     Execution},
  author = {Mishra, Mahim and Callahan, Timothy J and Chelcea, Tiberiu
     and Venkataramani, Girish and Budiu, Mihai and Goldstein, Seth
     Copen},
  booktitle = {12th ACM International Conference on Architecture
     Support for Programming Languages and Operating Systems
     (ASPLOS)},
  year = {2006},
  pages = {163--174},
  address = {San Jose, CA},
  month = {Oct},
  abstract = {Spatial Computing (SC) has been shown to be an
     energy-efficient model for implementing program kernels. In this
     paper we explore the feasibility of using SC for more than small
     kernels. To this end, we evaluate the performance and energy
     efficiency of entire applications on Tartan, a general-purpose
     architecture which integrates a reconfigurable fabric (RF) with a
     superscalar core. Our compiler automatically partitions and
     compiles an application into an instruction stream for the core
     and a configuration for the RF. We use a detailed simulator to
     capture both timing and energy numbers for all parts of the
     system. \par Our results indicate that a hierarchical RF
     architecture, designed around a scalable interconnect, is
     instrumental in harnessing the benefits of spatial computation.
     The interconnect uses static configuration and routing at the
     lower levels and a packet-switched, dynamically-routed network at
     the top level. Tartan is most energy-efficient when almost all of
     the application is mapped to the RF, indicating the need for the
     RF to support most general-purpose programming constructs. Our
     initial investigation reveals that such a system can provide, on
     average, an order of magnitude improvement in energy-delay
     compared to an aggressive superscalar core on single-threaded
     workloads.},
  keywords = {Asychronous Circuits, Spatial Computing, Reconfigurable
     Computing,Phoenix, Tartan},
  url = {http://www.cs.cmu.edu/~seth/papers/mahim-asplos06.pdf},
}

@inproceedings{derosa-rss06,
  author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
     and Campbell, Jason D. and Pillai, Padmanabhan},
  booktitle = {Robotics: Science and Systems Workshop on
     Self-Reconfigurable Modular Robots},
  title = {Distributed Watchpoints: Debugging Very Large Ensembles of
     Robots},
  month = {Aug},
  year = {2006},
  keywords = {Claytronics, Modular Robotics, Debugging, Distributed
     Systems},
  address = {Philadelphia, PA},
  talk = {http://www.cs.cmu.edu/~seth/papers/derosa-rss06.pdf},
  url = {http://www.cs.cmu.edu/~seth/papers/derosa-rss06.pdf},
  abstract = {We describe a debugging tool for modular robotics that
     introduces the concept of distributed watchpoint triggers. This
     technique can initiate debugging actions (system halt, global
     snapshot, logging, etc.) in an ensemble of robots based on
     temporal, physical, and logical conditions distributed over
     multiple robots. Our technique is specifically designed to be
     effective in debugging modular robotic ensembles, where many
     important types of failure conditions can be detected within
     small, physically connected subsets of the total ensemble.},
}

@techreport{venkataramani-tr06,
  author = {Venkataramani, Girish and Chelcea, Tiberiu and Budiu,
     Mihai and Goldstein, Seth Copen},
  title = {Modeling the Global Critical Path in Concurrent Systems},
  institution = {Carnegie Mellon University},
  year = {2006},
  number = {CMU-CS-06-144},
  month = {Aug},
  abstract = {We show how the global critical path can be used as a
     practical tool for understanding, optimizing and summarizing the
     behavior of highly concurrent self-timed circuits. Traditionally,
     critical path analysis has been applied to DAGs, and thus was
     constrained to combinatorial sub-circuits. We formally define the
     global critical path (GCP) and show how it can be constructed
     using only local information that is automatically derived
     directly from the circuit. We introduce a form of Production
     Rules, which can accurately determine the GCP for a given input
     vector, even for modules which exhibit choice and early
     termination. \par The GCP provides valuable insight into the
     control behavior of the application, which help in formulating
     new optimizations and re-formulating existing ones to use the GCP
     knowledge. We have constructed a fully automated framework for
     GCP detection and analysis, and have incorporated this framework
     into a high-level synthesis tool-chain. We demonstrate the
     effectiveness of the GCP framework by re-formulating two
     traditional CAD optimizations to use the GCP, yielding efficient
     algorithms which improve circuit power (by up to 9\%) and
     performance (by up to 60\%) in our experiments.},
  keywords = {Asychronous Circuits, Spatial Computing,CAD, Global
     Critical Path},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-tr06.pdf},
}

@inproceedings{derosa-icra06,
  author = {De~Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
     and Campbell, Jason D. and Pillai, Padmanabhan},
  title = {Scalable Shape Sculpting via Hole Motion: Motion Planning
     in Lattice-Constrained Module Robots},
  month = {May},
  booktitle = {Proceedings of the 2006 {IEEE} International Conference
     on Robotics and Automation (ICRA '06)},
  year = {2006},
  keywords = {Claytronics, Programmable Matter, Planning, Modular
     Robotics},
  url = {http://www.cs.cmu.edu/~seth/papers/derosa-icra06.pdf},
  abstract = {We describe a novel shape formation algorithm for
     ensembles of 2-dimensional lattice-arrayed modular robots, based
     on the manipulation of regularly shaped voids within the lattice
     (``holes''). The algorithm is massively parallel and fully
     distributed. Constructing a goal shape requires time propor-
     tional only to the complexity of the desired target geometry.
     Construction of the shape by the modules requires no global
     communication nor broadcast floods after distribution of the
     target shape. Results in simulation show 97.3\% shape compliance
     in ensembles of approximately 60,000 modules, and we believe that
     the algorithm will generalize to 3D and scale to handle millions
     of modules.},
}

@inproceedings{karagozler-rascal06,
  title = {Ultralight Modular Robotic Building blocks for the Rapid
     Deployment of Planetary Outposts},
  booktitle = {Revolutionary Aerospace Systems Concepts Academic
     Linkage (RASC-AL) Forum 2006},
  author = {Karagozler, Mustafa Emre and Kirby, Brian and Lee, W.J.
     and Marinelli, Eugene and Ng, T.C. and Weller, Michael and
     Goldstein, Seth Copen},
  year = {2006},
  month = {May},
  address = {Cape Canaveral, FL},
  url = {http://www.cs.cmu.edu/~seth/papers/karagozler-rascal06.pdf},
  keywords = {Claytronics,Modular Robotics,Robotics},
}

@techreport{koes-tr06,
  author = {Koes, David Ryan and Goldstein, Seth Copen},
  title = {An Analysis of Graph Coloring Register Allocation},
  institution = {Carnegie Mellon University},
  year = {2006},
  number = {CMU-CS-06-111},
  pages = {10},
  month = {Mar},
  url = {http://www.cs.cmu.edu/~seth/papers/koes-tr06.pdf},
  abstract = {Graph coloring is the de facto standard technique for
     register allocation within a compiler. In this paper we examine
     the importance of the quality of the coloring algorithm and
     various extensions of the basic graph coloring technique by
     replacing the coloring phase of the GNU compiler's register
     allocator with an optimal coloring algorithm. We then extend this
     optimal algorithm to incorporate various extensions such as
     coalescing and preferential register assignment. We find that
     using an optimal coloring algorithm has surprisingly little
     benefit and empirically demonstrate the benefit of the various
     extensions.},
  keywords = {Compilers:Register Allocation},
}

@inproceedings{koes-lctes06,
  author = {Koes, David Ryan and Goldstein, Seth Copen},
  title = {A Better Global Progressive Allocator},
  publisher = {Academia Press},
  url = {http://www.cs.cmu.edu/~seth/papers/koes-lctes06.pdf},
  booktitle = {LCTES 06 Student Poster Session},
  year = {2006},
  abstract = {We present an improvement to the simultaneous heuristic
     allocator component of the global progressive register allocator
     described in our previous work \cite{koes-pldi2006}. Our improved
     allocator decomposes the control flow graph into linear traces
     which are allocated in the same manner as a single basic block.
     We investigate two methods for handling the control flow within
     the traces both of which produce better quality allocations than
     the simultaneous heuristic allocator.},
  keywords = {Compilers:Register Allocation},
}

@inproceedings{koes-pldi2006,
  author = {Koes, David Ryan and Goldstein, Seth Copen},
  title = {A global progressive register allocator},
  booktitle = {Proceedings of the 2006 ACM SIGPLAN conference on
     Programming language design and implementation (PLDI'06)},
  year = {2006},
  isbn = {1-59593-320-4},
  pages = {204--215},
  doi = {http://doi.acm.org/10.1145/1133981.1134006},
  publisher = {ACM Press},
  address = {New York, NY},
  abstract = {This paper describes a {\em global progressive register
     allocator}, a register allocator that uses an expressive model of
     the register allocation problem to quickly find a good allocation
     and then progressively find better allocations until a provably
     optimal solution is found or a preset time limit is reached. The
     key contributions of this paper are an expressive model of global
     register allocation based on multi-commodity network flows that
     explicitly represents spill code optimization, register
     preferences, copy insertion, and constant rematerialization; two
     fast, but effective, heuristic allocators based on this model;
     and a more elaborate progressive allocator that uses Lagrangian
     relaxation to compute the optimality of its allocations. Our
     progressive allocator demonstrates code size improvements as
     large as 16.75\% compared to a traditional graph allocator. On
     average, we observe an initial improvement of 3.47\%, which
     increases progressively to 6.84\% as more time is permitted for
     compilation.},
  keywords = {Compilers:Register Allocation},
  url = {http://www.cs.cmu.edu/~seth/papers/koes-pldi2006.pdf},
}

@article{venkataramani-tcad06,
  title = {Hardware Compilation of Application-Specific Memory Access
     Interconnect},
  author = {Venkataramani, Girish and Bjerregaard, Tobias and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  journal = {IEEE Transactions on Computer Aided Design of Integrated
     Circuits and Systems},
  year = {2006},
  volume = {25},
  number = {5},
  pages = {756--771},
  issn = {0278-0070},
  abstract = {{A major obstacle to successful high-level synthesis
     (HLS) of large-scale application-specified integrated circuit
     systems is the presence of memory accesses to a shared-memory
     subsystem. The latency to access memory is often not statically
     predictable, which creates problems for scheduling operations
     dependent on memory reads. More fundamental is that dependences
     between accesses may not be statically provable (e.g., if the
     specification language permits pointers), which introduces
     memory-consistency problems. Addressing these issues with static
     scheduling results in overly conservative circuits, and thus,
     most state-of-the-art HLS tools limit memory systems to those
     that have predictable latencies and limit programmers to
     specifications that forbid arbitrary memory-reference patterns. A
     new HLS framework for the synthesis and optimization of memory
     accesses (SOMA) is presented. SOMA enables specifications to
     include arbitrary memory references (e.g., pointers) and allows
     the memory system to incorporate features that might cause the
     latency of a memory access to vary dynamically. This results in
     raising the level of abstraction in the input specification,
     enabling faster design times. SOMA synthesizes a memory access
     network (MAN) architecture that facilitates dynamic scheduling
     and ordering of memory accesses. The paper describes a basic MAN
     construction technique that illustrates how dynamic ordering
     helps in efficiently maintaining memory consistency and how
     dynamic scheduling helps alleviate the variable-latency problem.
     Then, it is shown how static analysis of the access patterns can
     be used to optimize the MAN. One optimization changes the MAN
     interconnect topology to increase concurrence. A second
     optimization reduces the synchronization overhead necessary to
     maintain memory consistency. Postlayout experiments demonstrate
     that SOMA's application-specific MAN construction significantly
     improves power and performance for a range of benchmarks.}},
  keywords = {Asychronous Circuits, Spatial
     Computing,Phoenix,Network-on-a-chip},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-tcad06.pdf},
}

@inproceedings{venkataramani-iccad06,
  title = {Leveraging Protocol Knowledge in Slack Matching},
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM International Conference on Computer-Aided
     Design (ICCAD)},
  year = {2006},
  address = {San Jose, CA},
  month = {Nov},
  abstract = {{Stalls, due to mis-matches in communication rates, are
     a major performance obstacle in pipelined circuits. If the rate
     of data production is faster than the rate of consumption, the
     resulting design performs slower than when the communication rate
     is matched. This can be remedied by inserting pipeline buffers
     (to temporarily hold data), allowing the producer to proceed if
     the consumer is not ready to accept data. The problem of deciding
     which channels need these buffers (and how many) for an arbitrary
     communication profile is called the slack matching problem; the
     optimal solution to this problem has been shown to be
     NP-complete. \par In this paper, we present a heuristic that uses
     knowledge of the communication protocol to explicitly model these
     bottlenecks, and an iterative algorithm to progressively remove
     these bottlenecks by inserting buffers. We apply this algorithm
     to asynchronous circuits, and show that it naturally handles
     large designs with arbitrarily cyclic and acyclic topologies,
     which exhibit various types of control choice. The heuristic is
     efficient, achieving linear time complexity in practice, and
     produces solutions that (a) achieve up to 60\% performance
     speedup on large media processing kernels, and (b) can either be
     verified to be optimal, or the approximation margin can be
     bounded. }},
  keywords = {Asychronous Circuits, Spatial Computing, CAD, Global
     Critical Path},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iccad06.pdf},
}

@inproceedings{goldstein05,
  author = {Goldstein, Seth Copen and Mowry, Todd C. and Campbell,
     Jason D. and Lee, Peter and Pillai, Padmanabhan and Hoburg, James
     F. and Gibbons, Phillip B. and Guestrin, Carlos and Kuffner,
     James and Kirby, Brian and Rister, Benjamin D. and De~Rosa,
     Michael and Funiak, Stanislav and Aksak, Burak and Sukthankar,
     Rahul},
  title = {The Ensemble Principle},
  booktitle = {13th Foresight Conference of Advanced Nanotechnogy},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein05.pdf},
  year = {2005},
  month = {Oct},
  address = {San Francisco, CA},
  keywords = {Claytronics, Robotics},
}

@inproceedings{venkataramani-isss05,
  title = {SOMA: A Tool for Synthesizing and Optimizing Memory
     Accesses in ASICs},
  author = {Venkataramani, Girish and Bjerregaard, Tobias and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM/IFIP International Conference on
     Hardware/Software Codesign and System Synthesis (CODES-ISSS)},
  year = {2005},
  isbn = {1-59593-161-9},
  pages = {231-236},
  address = {Jersey City, NJ, USA},
  month = {Sep},
  abstract = {Arbitrary memory dependencies and variable latency
     memory systems are major obstacles to the synthesis of
     large-scale ASIC systems in high-level synthesis. This paper
     presents SOMA, a synthesis framework for constructing Memory
     Access Network (MAN) architectures that inherently enforce memory
     consistency in the presence of dynamic memory access
     dependencies. A fundamental bottleneck in any such network is
     arbitrating between concurrent accesses to a shared memory
     resource. To alleviate this bottleneck, SOMA uses an
     application-specific concurrency analysis technique to predict
     the dynamic memory parallelism profile of the application. This
     is then used to customize the MAN architecture. Depending on the
     parallelism profile, the MAN may be optimized for latency,
     throughput or both. The optimized MAN is automatically
     synthesized into gate-level structural Verilog using a flexible
     library of network building blocks. SOMA has been successfully
     integrated into an automated C-to-hardware synthesis flow, which
     generates standard cell circuits from unrestricted ANSI-C
     programs. Post-layout experiments demonstrate that application
     specific MAN construction significantly improves power and
     performance.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix,
     CAD,Compilers:Memory Optimizations},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-isss05.pdf},
}

@inproceedings{campbell05,
  author = {Campbell, Jason D. and Pillai, Padmanabhan and Goldstein,
     Seth Copen},
  title = {The Robot is the Tether: Active, Adaptive Power Routing for
     Modular Robots With Unary Inter-robot Connectors},
  booktitle = {IEEE/RSJ International Conference on Intelligent Robots
     and Systems (IROS 2005)},
  pages = {4108--15},
  year = {2005},
  address = {Edmonton, Alberta Canada},
  month = {Aug},
  keywords = {Claytronics, Robotics},
  url = {http://www.cs.cmu.edu/~seth/papers/campbell05.pdf},
}

@inproceedings{kirby-aaai05,
  author = {Kirby, Brian and Campbell, Jason D. and Aksak, Burak and
     Pillai, Padmanabhan and Hoburg, James F. and Mowry, Todd C. and
     Goldstein, Seth Copen},
  title = {Catoms: Moving Robots Without Moving Parts},
  url = {http://www.cs.cmu.edu/~seth/papers/kirby-aaai05.pdf},
  booktitle = {AAAI (Robot Exhibition)},
  pages = {1730--1},
  year = {2005},
  month = {Jul},
  address = {Pittsburgh, PA},
  keywords = {Claytronics, Robotics},
}

@inproceedings{venkataramani-iwls05,
  title = {{HLS} Support for Unconstrained Memory Accesses},
  author = {Venkataramani, Girish and Chelcea, Tiberiu and Goldstein,
     Seth Copen},
  booktitle = {IEEE 14th International Workshop on Logic Synthesis
     (IWLS)},
  year = {2005},
  address = {Lake Arrowhead, CA},
  month = {Jun},
  abstract = {A major obstacle in high-level synthesis (HLS) of
     large-scale ASIC systems is memory access patterns. Typically,
     most state-of-the-art HLS tools impose constraints on the memory
     references in the source application, requiring them to exhibit
     predictable access patterns, and/or requiring dependencies
     between them to be statically determinable. This paper addresses
     the HLS problem when such constraints are relaxed. We present an
     analysis infrastructure that can be used within any HLS toolflow
     for synthesizing circuits from high-level abstractions, such as
     ANSI-C, where no assumptions can be made about memory access
     latencies, and where dependencies between memory references can
     only be disambiguated dynamically at runtime (pointer aliasing).
     We start by describing a generic framework to build a
     dependence-aware, fully distributed, although often conservative,
     memory-access network (MAN) for a given memory-dependence graph.
     Then, we propose a suite of optimizations to customize the MAN
     for the given specification. All these techniques guarantee
     memory coherency. Experimental results on Mediabench benchmarks,
     show that such an approach succeeds in maintaining high levels of
     parallelism, while ensuring memory coherency. The optimizations
     succeed in lowering the synchronization overhead by as much as
     4x.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iwls05.pdf},
}

@article{goldstein-computer05,
  author = {Goldstein, Seth Copen and Campbell, Jason D. and Mowry,
     Todd C.},
  title = {Programmable Matter},
  journal = {IEEE Computer},
  volume = {38},
  number = {6},
  pages = {99--101},
  year = {2005},
  month = {Jun},
  keywords = {Claytronics, Programmable Matter},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-computer05.pdf},
}

@techreport{koes-tr05,
  author = {Koes, David Ryan and Chelcea, Tiberiu and Onyeama, Charles
     and Goldstein, Seth Copen},
  title = {Adding Faster with Application Specific Early Termination},
  institution = {Carnegie Mellon University},
  year = {2005},
  number = {CMU-CS-05-101},
  pages = {20},
  month = {May},
  url = {http://www.cs.cmu.edu/~seth/papers/koes-tr05.pdf},
  abstract = {This paper presents a methodology for improving the
     speed of high-speed adders. As a starting point, a previously
     proposed method, called speculative completion, is used in which
     fast- terminating additions are automatically detected. Unlike
     the previous design, the method proposed in this paper is able to
     adapt dynamically to (1) application-specific behavior and (2) to
     adder- specific behavior, resulting in a higher detection rate of
     fast additions and, consequently, a faster average-case speed for
     addition. Our experimental results show detection rates of over
     99\%, and adder average-case speed improvements of up to 14.\%.},
  keywords = {Asychronous Circuits},
}

@inproceedings{beckett-iscas05,
  title = {Why area might reduce power in nanoscale CMOS},
  url = {http://www.cs.cmu.edu/~seth/papers/beckett-iscas05.pdf},
  booktitle = {IEEE International Symposium on Circuits and Systems,
     2005, (ISCAS 2005)},
  author = {Beckett, Paul and Goldstein, Seth Copen},
  year = {2005},
  pages = {2329-2332},
  volume = {3},
  month = {May},
  address = {Kobe, Japan},
  abstract = {In this paper we explore the relationship between power
     and area. By exploiting parallelism (and thus using more area)
     one can reduce the switching frequency allowing a reduction in
     VDD which results in a reduction in power. Under a scaling regime
     which allows threshold voltage to increase as VDD decreases we
     find that dynamic and subthreshold power loss in CMOS exhibit a
     dependence on area proportional to A^((\sigma^-3)/\sigma) while
     gate leakage power proportional to A^((\sigma^-6)/\sigma) and
     short circuit power A^((\sigma^-6)/\sigma). Thus, with the large
     number of devices at our disposal we can exploit techniques such
     as spatial computing--tailoring the program directly to the
     hardware--to overcome the negative effects of scaling. The value
     of s describes the effectiveness of the technique for a
     particular circuit and/or algorithm--for circuits that exhibit a
     value of \sigma <= 3, power will be a constant or reducing
     function of area. We briefly speculate on how \sigma might be
     influenced by a move to nanoscale technology.},
  keywords = {Electronic Nanotechnology,Power,Energy},
}

@misc{goldstein-popsci05,
  title = {2029 The 3-D Fax Machine Brings Back the House Call},
  howpublished = {Headline from the Future, Popular Science Magazine},
  author = {Goldstein, Seth Copen},
  year = {2005},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-popsci05.pdf},
  month = {Mar},
  pages = {34},
  keywords = {Claytronics},
}

@inproceedings{koes-cgo05,
  author = {Koes, David Ryan and Goldstein, Seth Copen},
  title = {A Progressive Register Allocator for Irregular
     Architectures},
  booktitle = {Proceedings of the International Symposium on Code
     Generation and Optimization {(CGO'05)}},
  month = {Mar},
  year = {2005},
  isbn = {0-7695-2298-X},
  pages = {269--280},
  doi = {http://dx.doi.org/10.1109/CGO.2005.4},
  publisher = {IEEE Computer Society},
  address = {Washington, DC},
  abstract = {Register allocation is one of the most important
     optimizations a compiler performs. Conventional graph-coloring
     based register allocators are fast and do well on regular,
     RISC-like, architectures, but perform poorly on irregular,
     CISC-like, architectures with few registers and non-orthogonal
     instruction sets. At the other extreme, optimal register
     allocators based on integer linear programming are capable of
     fully modeling and exploiting the peculiarities of irregular
     architectures but do not scale well. We introduce the idea of a
     \textit{progressive allocator} which finds an initial allocation
     of quality comparable to a conventional allocator, but as more
     time is allowed for computation the quality of the allocation
     approaches optimal. This paper presents a progressive register
     allocator which uses a multi-commodity network flow model to
     elegantly represent the intricacies of irregular architectures.
     We evaluate our allocator substituted for {\tt gcc}'s local
     register allocation pass.},
  keywords = {Compilers:Register Allocation},
  url = {http://www.cs.cmu.edu/~seth/papers/koes-cgo05.pdf},
}

@inproceedings{budiu-ispass05,
  author = {Budiu, Mihai and Artigas, Pedro V. and Goldstein, Seth
     Copen},
  title = {Dataflow: A Complement to Superscalar},
  booktitle = {IEEE International Symposium on Performance Analysis of
     Systems and Software (ISPASS)},
  month = {Mar},
  year = {2005},
  pages = {177--186},
  address = {Austin, TX},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-ispass05.pdf},
  abstract = {There has been a resurgence of interest in dataflow
     architectures, because of their potential for exploiting
     parallelism with low overhead. In this paper we analyze the
     performance of a class of static dataflow machines on integer
     media and control-intensive programs and we explain why a
     dataflow machine, even with unlimited resources, does not always
     outperform a superscalar processor on general-purpose codes,
     under the assumption that both machines take the same time to
     execute basic operations. We compare a program-specific dataflow
     machine with unlimited parallelism to a superscalar processor
     running the same program. While the dataflow machines provide
     very good performance on most data-parallel programs, we show
     that the dataflow machine cannot always take advantage of the
     available parallelism. Using the dynamic critical path we
     investigate the mechanisms used by superscalar processors to
     provide a performance advantage and their impact on a dataflow
     model.},
  confweb = {http://www.ispass.org/ispass2005},
  keywords = {Spatial Computing,Phoenix},
}

@inproceedings{budiu-odes05,
  title = {Inter-iteration Scalar Replacement in the Presence of
     Conditional Control Flow},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-odes05.pdf},
  booktitle = {3rd Workshop on Optimizations for DSO and Embedded
     Systems},
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  year = {2005},
  address = {San Jose, CA},
  month = {Mar},
  also = {CMU CS Technical Report, CMU-CS-04-103},
  keywords = {Phoenix,Compilers:Loop Optimizations,Compilers:Scalar
     Replacement},
}

@article{lincoln-tnano05,
  title = {Nonphotolithographic Nanoscale Memory Density Prospects},
  abstract = {Technologies are now emerging to construct
     molecular-scale electronic wires and switches using bottom-up
     self-assembly. This opens the possibility of constructing
     nanoscale circuits and memories where active devices are just a
     few nanometers square and wire pitches may be on the order of ten
     nanometers. The features can be defined at this scale without
     using photolithography. The available assembly techniques have
     relatively high defect rates compared to conventional
     lithographic integrated circuits and can only produce very
     regular structures. Nonetheless, with proper memory organization,
     it is reasonable to expect these technologies to provide memory
     densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
     power requirements under 0.6 W/Tb/s for random read operations.},
  url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
  journal = {IEEE Transactions on Nanotechnology},
  author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
     and Lincoln, Patrick},
  year = {2005},
  month = {Mar},
  volume = {4},
  issue = {2},
  pages = {215-228},
  keywords = {Fault and Defect Tolerance, electronic nanotechnology,
     memory density, memory organization, molecular electronics},
  doi = {10.1109/TNANO.2004.837849},
}

@inproceedings{aksak-sensys05,
  author = {Aksak, Burak and Bhat, Preethi Srinivas and Campbell,
     Jason D. and De~Rosa, Michael and Funiak, Stanislav and Gibbons,
     Phillip B. and Goldstein, Seth Copen and Guestrin, Carlos and
     Gupta, Ashish and Helfrich, Casey and Hoburg, James F. and Kirby,
     Brian and Kuffner, James and Lee, Peter and Mowry, Todd C. and
     Pillai, Padmanabhan and Ravichandran, Ram and Rister, Benjamin D.
     and Seshan, Srinivasan and Sitti, Metin and Yu, Haifeng},
  title = {Demo Abstract: Claytronics---highly scalable
     communications, sensing, and actuation networks.},
  booktitle = {Proceedings of the 3rd international conference on
     Embedded networked sensor systems (SenSys)},
  year = {2005},
  pages = {299},
  url = {http://www.cs.cmu.edu/~seth/papers/aksak-sensys05.pdf},
  doi = {http://doi.acm.org/10.1145/1098918.1098964},
  keywords = {Claytronics, Programmable Matter},
}

@inproceedings{goldstein-iccad05,
  title = {The impact of the nanoscale on computing systems},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-iccad05.pdf},
  booktitle = {IEEE/ACM International Conference on Computer-Aided
     Design, 2005 (ICCAD 2005)},
  author = {Goldstein, Seth Copen},
  year = {2005},
  pages = {655-661},
  address = {San Jose, CA},
  month = {Nov},
  keywords = {Electronic Nanotechnology,molecular electronics},
}

@inproceedings{goldstein-waci04,
  author = {Goldstein, Seth Copen and Mowry, Todd C.},
  title = {Claytronics: An Instance of Programmable Matter},
  booktitle = {Wild and Crazy Ideas Session of ASPLOS},
  year = {2004},
  month = {Oct},
  address = {Boston, MA},
  keywords = {Claytronics},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-waci04.pdf},
  abstract = {Programmable matter refers to a technology that will
     allow one to control and manipulate three-dimensional physical
     artifacts (similar to how we already control and manipulate
     two-dimensional images with computer graphics). In other words,
     programmable matter will allow us to take a (big) step beyond
     virtual reality, to synthetic reality, an environment in which
     all the objects in a user's environment (including the ones
     inserted by the computer) are physically realized. Note that the
     idea is not to transport objects nor is it to recreate an objects
     chemical composition, but rather to create a physical artifact
     that will mimic the shape, movement, visual appearance, sound,
     and tactile qualities of the original object.},
}

@inproceedings{budiu-asplos04,
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  title = {Spatial Computation},
  booktitle = {International Conference on Architectural Support for
     Programming Languages and Operating Systems (ASPLOS)},
  pages = {14--26},
  month = {Oct},
  address = {Boston, MA},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-asplos04.pdf},
  abstract = {This paper describes a computer architecture that relies
     on the direct translation of high-level language programs into
     {\em Spatial Computation} (SC) hardware structures. SC program
     implementations are completely distributed, without any
     centralized control. SC circuits are optimized for {\em wires} at
     the expense of computation units. \par In this paper we
     investigate a particular implementation SC structures called ASH
     (Application-Specific Hardware). Under the assumption that
     computation is cheaper than communication, ASH replicates
     computation units to simplify interconnect, building a system
     which uses very simple, completely dedicated communication
     channels. As a consequence, communication on the datapath never
     requires arbitration; the only arbitration required is for
     accessing memory. ASH relies on very simple hardware primitives,
     using no associative structures, no multiported register files,
     no scheduling logic, no broadcast, and no clocks. As a
     consequence, ASH hardware is fast and extremely power efficient.
     \par In this work we demonstrate three features of ASH: (1) that
     such architectures can be built by automatic compilation of C
     programs, (2) that distributed computation is in some respects
     fundamentally different from monolithic superscalar processors
     and (3) that ASIC implementations of ASH use 3 orders of
     magnitude less energy compared to high-end superscalar
     processors, while being within a factor of two in performance.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix},
}

@misc{patent06,
  author = {Goldstein, Seth Copen and Rosewater, Daniel L.},
  title = {Methods of chemically assembled electronic nanotechnology
     circuit fabrication},
  howpublished = {United States Patent No. 7,064,000. Issued June 20,
     2006},
  month = {Jul},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/patent06.pdf},
  keywords = {Molecular Electronics,Two-Terminal Devices},
  abstract = {Chemically assembled electronic nanotechnology (CAEN)
     provides an alternative to using Complementary Metal Oxide
     Semiconductor (CMOS) for constructing circuits with feature sizes
     in the tens of nanometers. A molecular latch and a method using
     the latch that enables it to act as a state holding device,
     perform voltage restoration, and to provide I/O isolation is
     disclosed.},
  url = {http://www.cs.cmu.edu/~seth/papers/patent06.pdf},
}

@inproceedings{venkataramani-iwls04,
  title = {{C} to Asynchronous Dataflow Circuits: An End-to-End
     Toolflow},
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  booktitle = {IEEE 13th International Workshop on Logic Synthesis
     (IWLS)},
  address = {Temecula, CA},
  month = {Jun},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iwls04.pdf},
  abstract = {We present a complete toolflow that translates ANSI-C
     programs into asynchronous circuits. The toolflow is built around
     a compiler that converts C into a functional dataflow
     intermediate representation, exposing instruction-level, pipeline
     and memory parallelism. The compiler performs optimizations and
     converts the intermediate representation into pipelined
     asynchronous circuits, with no centralized controllers. In the
     resulting circuits, control is distributed, communication is
     achieved through local wires, and arbitration for datapath
     resources is unnecessary. Circuits automatically synthesized from
     Mediabench kernels exhibit substantially better energy-delay than
     either single-issue processors or aggressive superscalar cores.},
  keywords = {Asychronous Circuits,Spatial Computing,Phoenix,CAD},
}

@inproceedings{goldstein04-ersa04,
  author = {Goldstein, Seth Copen},
  title = {Computing Without Processors},
  booktitle = {International Conference on Engineering of
     Reconfigurable Systems and Algorithms (ERSA'04)},
  abstract = {The continuation of the remarkable exponential increases
     in processing power over the recent past faces imminent
     challenges due in part rising cost of design and manufacturing
     and the physics of deep-submicron semiconductor devices. In this
     talk we will discuss a promising alternative to ever more complex
     processors, application specific hardware (ASH). The ASH model is
     based on compiling high-level programs directly into circuits,
     which can either be fabricated as ASICs or more reasonably
     converted in configurations for reconfigurable devices. We will
     discuss the challenges involved in compiling sequential
     programming languages into circuits and the challenges in
     implementing those circuits in a scalable and power efficient
     manner.},
  address = {Las Vegas, NV},
  month = {Jun},
  year = {2004},
  pages = {29--32},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology,
     Fault and Defect Tolerance},
}

@inproceedings{koes-msp2004,
  author = {Koes, David Ryan and Budiu, Mihai and Venkataramani,
     Girish and Goldstein, Seth Copen},
  title = {Programmer Specified Pointer Independence},
  booktitle = {Proceedings of the 2004 workshop on Memory system
     performance (MSP)},
  month = {Jun},
  year = {2004},
  isbn = {1-58113-941-1},
  pages = {51--59},
  address = {Washington, D.C.},
  doi = {http://doi.acm.org/10.1145/1065895.1065905},
  also = {Carnegie Mellon University TR CMU-CS-03-123},
  url = {http://www.cs.cmu.edu/~seth/papers/koes-msp2004.pdf},
  confweb = {http://cs.anu.edu.au/~Steve.Blackburn/msp2004},
  publisher = {ACM Press},
  abstract = {Good alias analysis is essential in order to achieve
     high performance on modern processors, yet precise
     interprocedural analysis does not scale well. We present a source
     code annotation, {\tt \#pragma independent}, which provides
     precise pointer aliasing information to the compiler, and
     describe a tool which highlights the most important and most
     likely correct locations at which a programmer should insert
     these annotations. Using this tool we perform a limit study on
     the effectiveness of pointer independence in improving program
     performance through improved compilation.},
  keywords = {Compilers:Alias Analysis,Phoenix},
}

@inproceedings{budiu-async04,
  title = {Translating ANSI C to Asynchronous Circuits},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
  booktitle = {10th IEEE International Symposium on Asynchronous
     Circuits and Systems (ASYNC '04)},
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  address = {Crete, Greece},
  year = {2004},
  month = {Apr},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
     Computing},
}

@inproceedings{goldstein-gomac04,
  title = {The Challenges and Opportunities of Nanoelectronics},
  author = {Goldstein, Seth Copen},
  booktitle = {Proceedings of Government Microcircuit Applications and
     Critical Technology Conference (GOMAC Tech 04)},
  year = {2004},
  address = {Monterey, CA},
  keywords = {Electronic Nanotechnology},
  month = {Mar},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-gomac04.pdf},
}

@incollection{mishra-nqmc04,
  title = {Defect Tolerance at the End of the Roadmap},
  booktitle = {Nano, Quantum and Molecular Computing: Implications to
     High Level Design and Validation},
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  year = {2004},
  editor = {Sandeep K. Shukla and R. Iris Bahar},
  publisher = {Kluwer Academic Publishers},
  isbn = {1-4020-80670},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Reconfigurable Computing,Phoenix,molecular
     electronics},
}

@inproceedings{goldstein-robosphere04,
  author = {Goldstein, Seth Copen and Mowry, Todd C.},
  title = {Claytronics: A scalable basis for future robots},
  booktitle = {RoboSphere 2004},
  address = {Moffett Field, CA},
  month = {Nov},
  year = {2004},
  keywords = {Claytronics, Robotics},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-robosphere04.pdf},
}

@techreport{budiu-tr04,
  title = {Inter-Iteration Scalar Replacement in the Presence of
     Conditional Control-Flow},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr04.pdf},
  booktitle = {CMU CS Technical Report, CMU-CS-04-103},
  month = {Feb},
  year = {2004},
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  institution = {Carnegie Mellon University},
  see = {budiu-odes05},
  keywords = {Phoenix,Compilers:Loop Optimizations,Compilers:Scalar
     Replacement},
}

@inproceedings{mishra-itc03,
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  title = {Defect Tolerance at the End of the Roadmap},
  booktitle = {Proceedings of the International Test Conference
     ({ITC}), 2003},
  month = {Sep},
  year = {2003},
  address = {Charlotte, {NC}},
  url = {http://www.cs.cmu.edu/~seth/papers/mishra-itc03.pdf},
  abstract = {Defect tolerance will become more important as feature
     sizes shrink closer to single digit nanometer dimensions. This is
     true whether the chips are manufactured using top-down methods
     (e.g., photolithography) or bottom-up methods (e.g., chemically
     assembled electronic nanotechnology, or CAEN). In this paper, we
     propose a defect tolerance methodology centered around
     reconfigurable devices, a scalable testing method, and dynamic
     place-and-route. Our methodology is particularly well suited for
     CAEN.},
  keywords = {Spatial Computing, Reconfigurable
     Computing,Phoenix,Fault and Defect Tolerance},
}

@inproceedings{goldstein-inano03,
  title = {Models and Abstractions for Nanoelectronics},
  booktitle = {Third IEEE Conference on Nanotechnology (IEEE-NANO
     2003)},
  author = {Goldstein, Seth Copen and Zhu, Y},
  address = {San Francisco, CA},
  year = {2003},
  month = {Aug},
  keywords = {Electronic Nanotechnology},
}

@inproceedings{goldstein-asap03,
  title = {Reconfigurable Computing and Electronic Nanotechnology},
  author = {Goldstein, Seth Copen and Budiu, Mihai and Mishra, Mahim
     and Venkataramani, Girish},
  booktitle = {Proceedings of the {IEEE} 14th International Conference
     on Application-specific Systems, Architectures and Processors
     ({ASAP} 2003)},
  year = {2003},
  address = {The Hague, Netherlands},
  month = {Jun},
  note = {Invited paper},
  pages = {132-143},
  abstract = {In this paper we examine the opportunities brought about
     by recent progress in electronic nanotechnology and describe the
     methods needed to harness them for building a new computer
     architecture. In this process we decompose some traditional
     abstractions, such as the transistor, into fine-grain pieces,
     such as signal restoration and input-output isolation. We also
     show how we can forgo the extreme reliability of CMOS circuits
     for low-cost chemical self-assembly at the expense of large
     manufacturing defect densities. We discuss advanced testing
     methods which can be used to recover perfect functionality from
     unreliable parts. We proceed to show how the molecular switch,
     the regularity of the circuits created by self-assembly and the
     high defect densities logically require the use of reconfigurable
     hardware as a basic building block for hardware design. We then
     capitalize on the convergence of compilation and hardware
     synthesis (which takes place when programming reconfigurable
     hardware) to propose the complete elimination of the
     instruction-set architecture from the system architecture, and
     the synthesis of asynchronous dataflow machines directly from
     high-level programming languages, such as C. We discuss in some
     detail a scalable compilation system that perform this task.},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asap03.pdf},
}

@inproceedings{mishra-itsw03,
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  title = {Defect Tolerance After the Roadmap},
  booktitle = {Proceedings of the 10th International Test Synthesis
     Workshop (ITSW)},
  month = {Mar},
  year = {2003},
  address = {Santa Barbara, {CA}},
  keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
     Fault and Defect Tolerance},
  url = {http://www.cs.cmu.edu/~seth/papers/mishra-itsw03.pdf},
}

@inproceedings{budiu-cgo03,
  title = {Optimizing Memory Accesses For Spatial Computation},
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  booktitle = {Proceedings of the 1st International ACM/IEEE Symposium
     on Code Generation and Optimization (CGO 03)},
  year = {2003},
  address = {San Francisco, CA},
  month = {Mar},
  pages = {216-227},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-cgo03.pdf},
  keywords = {Spatial Computing, Reconfigurable
     Computing,Phoenix,Compilers:Memory Optimizations},
}

@inproceedings{goldstein-hldvt03,
  title = {Reconfigurable Nanoelectronics and Defect Tolerance},
  author = {Goldstein, Seth Copen},
  booktitle = {Proceedings of High-level design, verification, and
     test},
  year = {2003},
  keywords = {Reconfigurable Computing, Electronic Nanotechnology,
     Fault and Defect Tolerance},
}

@article{mircea-ieee03,
  title = {Molecular Electronics: From Devices and Interconnect to
     Circuits and Architecture},
  author = {Stan, Mircea R and Franzon, Paul D and Goldstein, Seth
     Copen and Lach, John C and Ziegler, Matthew M},
  journal = {Proceedings of the IEEE},
  year = {2003},
  volume = {91},
  number = {11},
  month = {Nov},
  keywords = {Electronic Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/mircea-ieee03.pdf},
}

@inproceedings{shukla-hldvt03,
  title = {Nano, Quantum, and Molecular Computing: Are We Ready for
     the Validation and Test Challenges},
  url = {http://www.cs.cmu.edu/~seth/papers/shukla-hldvt03.pdf},
  talk = {http://www.cs.cmu.edu/~seth/hldvt03-goldstein.pdf},
  booktitle = {Eighth IEEE International High-Level Design Validation
     and Test Workshop},
  author = {Shukla, Sandeep K. and Karri, Ramesh and Goldstein, Seth
     Copen and Brewer, Forest and Banerjee, Kaustav and Basu, Sankar},
  year = {2003},
  month = {Nov},
  pages = {307},
  address = {San Francisco, CA},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,molecular electronics},
}

@incollection{goldstein-mn03,
  title = {Molecules, Gates, Circuits, Computer},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
  booktitle = {Molecular Nanoelectronics},
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  year = {2003},
  editor = {Mark A. Reed and Takhee Lee},
  publisher = {American Scientific Publishers},
  address = {Stevenson Ranch, CA},
  month = {Jan},
  isbn = {1-588883-006-3},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Reconfigurable Computing,Spatial
     Computing,electronic nanotechnology,molecular electronics},
}

@inproceedings{budiu-fpl02,
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  title = {Compiling Application-Specific Hardware},
  booktitle = {Proceedings of the 12th International Conference on
     Field Programmable Logic and Applications},
  year = {2002},
  address = {Montpellier (La Grande-Motte), France},
  month = {Sep},
  pages = {853--863},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-fpl02.pdf},
  abstract = {In this paper we describe ASH, an architectural
     framework for implementing Application-Specific Hardware. ASH is
     based on automatic hardware synthesis from high-level languages.
     The generated circuits use only localized computation structures;
     in consequence, we expect these circuits to be fast, to use
     little power and to scale well with program complexity. \par We
     present in detail CASH, a scalable compiler framework for ASH,
     which generates hardware from programs written in C. Our compiler
     exploits instruction level parallelism by using aggressive
     speculation and dynamic scheduling. Based on this compilation
     scheme, we evaluate the computational resources necessary for
     implementing complex integer-based programs, and we suggest
     architectural features that would support the ASH framework.},
  keywords = {Spatial Computing,Phoenix,Compilers:CASH},
}

@inproceedings{venkataramani-fpl02,
  title = {Factors Influencing the Performance of a CPU-RFU Hybrid
     Architecture},
  author = {Venkataramani, Girish and Sudhir, Suraj and Budiu, Mihai
     and Goldstein, Seth Copen},
  booktitle = {Proceedings of the 12th International Conference on
     Field Programmable Logic and Applications (FPL)},
  year = {2002},
  address = {Montpellier (La Grande-Motte), France},
  month = {Sep},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-fpl02.pdf},
  abstract = {Closely coupling a reconfigurable fabric with a
     conventional processor has been shown to successfully improve the
     system performance. However, today s superscalar pro-cessors are
     both complex and adept at extracting Instruction Level
     Parallelism (ILP), which introduces many complex issues to the
     design of a hybrid CPU-RFU system. This paper examines the design
     of a superscalar processor augmented with a closely-coupled
     recon-figurable fabric. It identifies architectural and compiler
     issues that affect the performance of the overall system.
     Previous efforts at combining a processor core with a
     reconfigurable fabric are examined in the light of these issues.
     We also present simulation results that emphasize the impact of
     these factors.},
  pages = {955-965},
  isbn = {3-540-44108-5},
  publisher = {Springer-Verlag},
  keywords = {Spatial Computing,Reconfigurable Computing,Phoenix},
}

@techreport{rg01,
  author = {Rosewater, Daniel L. and Goldstein, Seth Copen},
  title = {What makes a good molecular computing device?},
  institution = {Carnegie Mellon University},
  year = {2002},
  number = {CMU-CS-02-181},
  month = {Sep},
  keywords = {Electronic Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/rg01.pdf},
}

@inproceedings{goldstein-cra02,
  title = {Assembly And Differentiation},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-cra02.pdf},
  booktitle = {CRA Conference on Grand Research Challenges},
  author = {Goldstein, Seth Copen},
  address = {Warrenton, Virginia},
  year = {2002},
  month = {Jun},
  keywords = {Programmable Matter},
}

@techreport{budiu-tr02,
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  title = {Pegasus: An Efficient Intermediate Representation},
  institution = {Carnegie Mellon University},
  year = {2002},
  number = {CMU-CS-02-107},
  month = {May},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr02.pdf},
  pages = {20},
  abstract = {We present Pegasus, a compact and expressive
     intermediate representation for imperative languages. The
     representation is suitable for target architectures supporting
     predicated execution and aggressive speculation. In Pegasus
     information about the global dataflow of the program is encoded
     in local structures, enabling compact and efficient algorithms
     for program optimizations. As a proof of the versatility of
     Pegasus, we have used it in a compiler translating C programs to
     hardware implementations.},
  keywords = {Spatial Computing, Reconfigurable Computing,Phoenix},
}

@inproceedings{yan-fccm02,
  author = {Yan, Rong and Goldstein, Seth Copen},
  title = {Memory: Improving Memory Locality in Very Large
     Reconfigurable Fabrics},
  booktitle = {Proceedings of 2002 IEEE Symposium on
     Field-Programmable Custom Computing Machines (FCCM)},
  year = {2002},
  address = {Napa Valley, CA},
  month = {Apr},
  url = {http://www.cs.cmu.edu/~seth/papers/yan-fccm02.pdf},
  keywords = {Reconfigurable Computing},
}

@misc{patent04,
  author = {Goldstein, Seth Copen and Rosewater, Daniel L.},
  title = {Molecular scale latch and associated clocking scheme to
     provide gain, memory and I/O isolation},
  howpublished = {United States Patent No. 6,777,982. Issued August
     17, 2004},
  month = {Apr},
  url = {http://www.cs.cmu.edu/~seth/papers/patent04.pdf},
  year = {2002},
  keywords = {Molecular Electronics,Two-Terminal Devices},
  abstract = {Chemically assembled electronic nanotechnology (CAEN)
     provides an alternative to using Complementary Metal Oxide
     Semiconductor (CMOS) for constructing circuits with feature sizes
     in the tens of nanometers. A molecular latch and a method using
     the latch that enables it to act as a state holding device,
     perform voltage restoration, and to provide I/O isolation is
     disclosed.},
  url = {http://www.cs.cmu.edu/~seth/papers/patent04.pdf},
}

@inproceedings{budiu-fccm02,
  author = {Budiu, Mihai and Mishra, Mahim and Bharambe, Ashwin and
     Goldstein, Seth Copen},
  title = {Peer-to-peer Hardware-Software Interfaces for
     Reconfigurable Fabrics},
  booktitle = {Proceedings of 2002 IEEE Symposium on
     Field-Programmable Custom Computing Machines (FCCM)},
  year = {2002},
  month = {Apr},
  pages = {57-66},
  address = {Napa Valley, CA},
  abstract = {In this paper we describe a peer-to-peer interface
     between processor cores and reconfigurable fabrics. The main
     advantage of the peer-to-peer model is that it greatly expands
     the scope of application for reconfigurable computing and hence
     its potential benefits. The primary extension in our model is
     that ``code'' on the reconfigurable hardware unit is allowed to
     invoke routines both on the reconfigurable unit itself and on the
     fixed logic processor. We describe the software constructs and
     compilation mechanisms needed for such an architecture, including
     a detailed description of the interface between the two parts of
     the application.},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-fccm02.pdf},
  keywords = {Reconfigurable Computing},
}

@inproceedings{mishra_goldstein_nsc1,
  author = {Mishra, Mahim and Goldstein, Seth Copen},
  title = {Scalable Defect Tolerance for Molecular Electronics},
  booktitle = {Proceedings of the 1st Workshop on Non-Silicon
     Computing (NSC-1)},
  address = {{Cambridge, MA}},
  year = {2002},
  url = {http://www.cs.cmu.edu/~seth/papers/mishra_goldstein_nsc1.pdf},
  abstract = {Chemically assembled electronic nanotechnology (CAEN) is
     a promising alternative to CMOS-based computing. However,
     CAEN-based circuits are expected to have huge defect densities.
     To solve this problem CAEN can be used to build reconfigurable
     fabrics which, assuming the defects can be found, are inherently
     defect tolerant. In this paper, we propose a scalable testing
     methodology for finding defects in reconfigurable devices.},
  keywords = {Reconfigurable Computing, Phoenix,Fault and Defect
     Tolerance},
}

@inproceedings{micro02,
  title = {From Molecules to Computers},
  author = {Goldstein, Seth Copen},
  year = {2002},
  address = {Istanbul, Turkey},
  booktitle = {Tutorial at 35th Annual International Symposium on
     Microarchitecture (Micro 35)},
  note = {Invited Tutorial},
  url = {http://www.cs.cmu.edu/~seth/papers/micro02.pdf},
  month = {Nov},
  keywords = {Electronic Nanotechnology},
}

@inproceedings{butts-iccad02,
  title = {Molecular electronics: devices, systems and tools for
     gigagate,gigabit chips},
  url = {http://www.cs.cmu.edu/~seth/papers/butts-iccad02.pdf},
  doi = {http://doi.ieeecomputersociety.org/10.1109/ICCAD.2002.1167569},
  booktitle = {International Conference on Computer-Aided Design (
     ICCAD '02)},
  author = {Butts, Michael and DeHon, Andre and Goldstein, Seth
     Copen},
  abstract = {New electronics technologies are emerging which may
     carry us beyond the limits of lithographic processing down to
     molecular-scale feature sizes. Devices and interconnects can be
     made from a variety of molecules and materials including bistable
     and switchable organic molecules, carbon nanotubes, and,
     single-crystal semiconductor nanowires. They can be
     self-assembled into organized structures and attached onto
     lithographic substrates. This tutorial reviews emerging
     molecular-scale electronics technology for CAD and system
     designers and highlights where ICCAD research can help support
     this technology.},
  address = {San Jose, CA},
  year = {2002},
  pages = {433-440},
  note = {invited tutorial at},
  month = {Nov},
  keywords = {Electronic Nanotechnology,Reconfigurable
     Computing,molecular electronics},
}

@inproceedings{isscc02,
  author = {Rosewater, Dan and Goldstein, Seth Copen},
  title = {Digital Logic Using Molecular Electronics},
  booktitle = {IEEE International Solid-State Circuits Conference
     (ISSCC)},
  year = {2002},
  month = {Feb},
  address = {San Francisco, CA},
  keywords = {Electronic Nanotechnology,Molecular
     Electronics,Two-Terminal Devices},
  url = {http://www.cs.cmu.edu/~seth/papers/isscc02.pdf},
}

@inproceedings{sudhir-fpl01,
  author = {Sudhir, Suraj and Nath, Suman and Goldstein, Seth Copen},
  title = {Configuration Caching and Swapping},
  year = {2001},
  booktitle = {11th International Conference on Field Programmable
     Logic and Applications},
  address = {Belfast, Northern Ireland},
  month = {Aug},
  keywords = {Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/sudhir-fpl01.pdf},
}

@inproceedings{cadambi-fpl01,
  title = {Static Profile-driven Compilation for FPGAs},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpl01.pdf},
  booktitle = {Proceedings of the 11th International Conference on
     Field-Programmable Logic and Applications},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  address = {Belfast, Northern Ireland},
  year = {2001},
  month = {Aug},
  keywords = {CAD,Reconfigurable Computing},
}

@inproceedings{goldstein-isca01,
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  title = {{NanoFabrics}: Spatial Computing Using Molecular
     Electronics},
  booktitle = {Proceedings of the 28th International Symposium on
     Computer Architecture (ISCA)},
  month = {Jul},
  address = {{G\"{o}teborg, Sweden}},
  year = {2001},
  pages = {178--189},
  abstract = {The continuation of the remarkable exponential increases
     in processing power over the recent past faces imminent
     challenges due in part to the physics of deep-submicron CMOS
     devices and the costs of both chip masks and future fabrication
     plants. A promising solution to these problems is offered by an
     alternative to CMOS-based computing, chemically assembled
     electronic nanotechnology (CAEN). In this paper we outline how
     CAEN based computing can become a reality. We briefly describe
     recent work in CAEN and how CAEN will affect computer
     architecture. We show how the inherently reconfigurable natures
     of CAEN devices can be exploited to provide high-density chips
     with defect tolerance which will significantly reduce the cost of
     manufacturing. After developing the basic building blocks of a
     CAEN based computing devices we present some preliminary results
     which indicate that CAEN based computing devices can meet or
     exceed the performance of CMOS based devices.},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca01.pdf},
  keywords = {Spatial Computing, Reconfigurable Computing,Phoenix,
     Electronic Nanotechnology},
}

@inproceedings{goldstein-wvlsi01,
  title = {Electronic Nanotechnology and Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-wvlsi01.pdf},
  booktitle = {Proceedings of the IEEE Computer Society Workshop VLSI
     2001},
  author = {Goldstein, Seth Copen},
  year = {2001},
  pages = {10},
  month = {Apr},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Reconfigurable Computing},
}

@inproceedings{goldstein-foresight01,
  author = {Goldstein, Seth Copen and Ellenbogen, James and Almassiam,
     David and Brown, Matt and Cannarsa, Mark and Klein, Jesse and
     Schell, Schuyler and Washburn, Geoff and Ziegler, Matthew M},
  title = {MolSpice: Designing Molecular Logic Circuits},
  booktitle = {Ninth Foresight Conference on Molecular
     Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-foresight01.pdf},
  year = {2001},
  month = {Nov},
  address = {Santa Clara, CA},
  keywords = {Electronic Nanotechnology, Molecular Electronics, CAD},
}

@inproceedings{cadambi-iccd00,
  title = {Efficient Place and Route for Pipeline Reconfigurable
     Architectures},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-iccd00.pdf},
  booktitle = {ICCD '00},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  address = {Austin, TX},
  year = {2000},
  month = {Sep},
  keywords = {CAD,Place and Route},
}

@inproceedings{budiu-europar00,
  title = {{BitValue} Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  author = {Budiu, Mihai and Sakr, Majd and Walker, Kevin and
     Goldstein, Seth Copen},
  booktitle = {Proceedings of the 2000 Europar Conference},
  year = {2000},
  volume = {1900},
  pages = {969--979},
  month = {Aug},
  issn = {0302-9743},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer Verlag},
  address = {Munich, Germany},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-europar00.pdf},
  also = {CMU CS Technical Report, CMU-CS-00-141, October 2000.},
  abstract = {We present a compiler algorithm called BitValue, which
     can discover both unused and constant bits in dusty-deck C
     programs. BitValue uses forward and backward dataflow analyses,
     generalizing constant-folding and dead-code detection at the
     bit-level. This algorithm enables compiler optimizations which
     target special processor architectures for computing on
     non-standard bitwidths. Using this algorithm we show that up to
     31\% of the computed bytes are thrown away (for programs from
     SpecINT95 and Mediabench). A compiler for reconfigurable hardware
     uses this algorithm to achieve substantial reductions (up to
     20-fold) in the size of the synthesized circuits.},
  keywords = {Spatial Computing,Reconfigurable
     Computing,Phoenix,PipeRench,CAD},
}

@techreport{budiu-tr00,
  title = {BitValue Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr00.pdf},
  booktitle = {CMU CS Technical Report, CMU-CS-00-141},
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  institution = {Carnegie Mellon University},
  year = {2000},
  month = {Jun},
  see = {budiu-europar00},
  keywords = {CAD,Compilers:CASH,Reconfigurable Computing},
}

@inproceedings{KSS00,
  author = {Kamarchik, Peter M. and Sinha, Steven and Goldstein, Seth
     Copen},
  title = {Fault Tolerance in Run-time Reconfigurable Architectures},
  booktitle = {IEEE Symposium on FPGAs for Custom Computing Machines
     (FCCM '00)},
  year = {2000},
  month = {Apr},
  address = {Napa, CA},
  keywords = {PipeRench, Fault and Defect Tolerance},
}

@article{schmit-jvlsi00,
  author = {Schmit, Herman and Cadambi, Srihari and Moe, Matthew and
     Goldstein, Seth Copen},
  title = {Pipeline Reconfigurable FPGAs},
  journal = {Journal of VLSI Signal Processing Systems},
  volume = {33},
  month = {Apr},
  year = {2000},
  pages = {70-77},
  abstract = {While reconfigurable computing promises to deliver
     incomparable performance, it is still a marginal technology due
     to the high cost of developing and upgrading applications.
     Hardware virtualization can be used to significantly reduce both
     these costs. In this paper we describe the benefits of hardware
     virtualization, and show how it can be achieved using the
     technique of pipeline reconfiguration. The result is PipeRench,
     an architecture that supports robust compilation and provides
     forward compatibility. Our preliminary performance analysis on
     PipeRench predicts that it will outperform commercial FPGAs and
     DSPs in both overall performance and in performance normalized
     for silicon area over a broad range of problem sizes.},
  number = {4},
  url = {http://www.cs.cmu.edu/~seth/papers/schmit-jvlsi00.pdf},
  doi = {},
  also = {chapter in Field-Programmable Custom Computing Technology:
     Architecture, Tools, and Applications},
  keywords = {PipeRench,Reconfigurable Computing},
}

@article{goldstein-ieee00,
  author = {Goldstein, Seth Copen and Schmit, Herman and Budiu, Mihai
     and Cadambi, Srihari and Moe, Matthew and Taylor, R. Reed},
  title = {{PipeRench}: A Reconfigurable Architecture and Compiler},
  journal = {IEEE Computer},
  year = {2000},
  volume = {33},
  number = {4},
  month = {Apr},
  pages = {70--77},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-ieee00.pdf},
  abstract = {With the proliferation of highly specialized embedded
     computer systems has come a diversification of workloads for
     computing devices. General-purpose processors are struggling to
     efficiently meet these applications' disparate needs, and custom
     hardware is rarely feasible. According to the authors,
     reconfigurable computing, which combines the flexibility of
     general-purpose processors with the efficiency of custom
     hardware, can provide the alternative. PipeRench and its
     associated compiler comprise the authors' new architecture for
     reconfigurable computing. Combined with a traditional digital
     signal processor, microcontroller or general-purpose processor,
     PipeRench can support a system's various computing needs without
     requiring custom hardware. The authors describe the PipeRench
     architecture and how it solves some of the pre-existing problems
     with FPGA architectures, such as logic granularity, configuration
     time, forward compatibility, hard constraints and compilation
     time.},
  keywords = {Reconfigurable Computing,PipeRench},
}

@inproceedings{sinha-fccm00,
  title = {Tunable Fault Tolerance for Runtime Reconfigurable
     Architectures},
  url = {http://www.cs.cmu.edu/~seth/papers/sinha-fccm00.pdf},
  booktitle = {8th IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM 2000)},
  author = {Sinha, Steven K. and Kamarchik, Peter M. and Goldstein,
     Seth Copen},
  abstract = {Fault tolerance is becoming an increasingly important
     issue, especially in mission-critical applications where data
     integrity is a paramount concern. Performance, however, remains a
     large driving force in the market place. Runtime reconfigurable
     hardware architectures have the power to balance fault tolerance
     with performance, allowing the amount of fault tolerance to be
     tuned at run-time. This paper describes a new built-in self-test
     designed to run on, and take advantage of, runtime reconfigurable
     architectures using the PipeRench architecture as a model. In
     addition, this paper introduces a new metric by which a user can
     set the desired fault tolerance of a runtime reconfigurable
     device},
  doi = {10.1109/FPGA.2000.903405},
  year = {2000},
  pages = {185-192},
  isbn = {0-7695-0871-5},
  address = {Napa Valley, CA},
  month = {Apr},
  keywords = {Fault And Defect Tolerance,PipeRench,Reconfigurable
     Computing},
}

@inproceedings{walker-fccm00,
  author = {Walker, Kevin and Budiu, Mihai and Goldstein, Seth Copen},
  title = {Interfacing Reconfigurable Logic with a {CPU}},
  booktitle = {2000 IEEE Symposium on Field-Programmable Custom
     Computing Machines},
  pages = {317--318},
  year = {2000},
  url = {http://www.cs.cmu.edu/~seth/papers/walker-fccm00.pdf},
  abstract = {Reconfigurable computing devices have achieved
     substantial performance improvements over conventional processors
     on some computational kernels. These benefits derive from
     hardware customization which avoids the mismatch between the
     basic requirements of the algorithms and the architectures of the
     processors. A reconfigurable fabric alone is not sufficient for
     general-purpose computing since it can be ill-suited to executing
     entire programs due to space limitations, dataflow-centricity,
     and inefficiency at implementing some operations (e.g.
     floating-point arithmetic). These observations have led to the
     appearance of numerous designs which place some form of
     reconfigurable logic under the control of a general-purpose
     processor. The authors explore the ways in which a reconfigurable
     fabric can be interfaced with a general-purpose processor. While
     off-chip reconfigurable fabrics have proven to be quite effective
     at performing streaming, data-intensive computations, they
     require large streams of data to overcome the latency between the
     devices. We explore the design space for an on-chip fabric, i.e.,
     a reconfigurable function unit (RFU). An RFU allows smaller
     portions of application to be mapped to the fabric in the form of
     custom instructions. Though the speedups achieved for stream
     based computations will in general be much larger than those for
     custom instructions, they are limited to a smaller class of
     applications. Custom instructions, however, can be found in a
     larger class of programs, and compiler techniques can
     automatically create them.},
  keywords = {Reconfigurable Computing},
}

@incollection{schmit-fpcct00,
  title = {Pipeline Reconfigurable FPGAs},
  url = {http://www.cs.cmu.edu/~seth/papers/schmit-fpcct00.pdf},
  booktitle = {Field-Programmable Custom Computing Technology:
     Architecture, Tools, and Applications},
  author = {Schmit, Herman and Goldstein, Seth Copen and Cadambi,
     Srihari and Moe, Matthew},
  year = {2000},
  editor = {Arnold, Jeffrey and Luk, Wayne and Pocek, Ken},
  publisher = {Kluwer Academic Publishers},
  isbn = {0-7923-7803-2},
  keywords = {PipeRench,Reconfigurable Computing},
}

@inproceedings{goldstein-asplos00,
  title = {NanoFabrics: Extending Moore's Law Beyond the CMOS Era},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-asplos00.pdf},
  booktitle = {The 10th International Conference on Architectural
     Support for Programming Languages and Operating Systems. (ASPLOS
     'IX)},
  author = {Goldstein, Seth Copen},
  address = {Cambridge, MA},
  year = {2000},
  month = {Nov},
  keywords = {Electronic Nanotechnology,Fault and Defect
     Tolerance,Molecular Electronics,Reconfigurable Computing},
}

@inproceedings{reed-ches99,
  author = {Taylor, R. Reed and Goldstein, Seth Copen},
  title = {A High-Performance Flexible Architecture for Cryptography},
  booktitle = {Proceedings of the Workshop on Cryptographic Hardware
     and Embedded Systems 1999 (CHES99)},
  address = {Worcester, MA},
  year = {1999},
  pages = {231-245},
  month = {Aug},
  abstract = {Cryptographic algorithms are more efficiently
     implemented in custom hardware than in software running on
     general-purpose processors. However, systems which use hardware
     implementations have significant drawbacks: they are unable to
     respond to flaws discovered in the implemented algorithm or to
     changes in standards. In this paper we show how reconfigurable
     computing offers high performance yet flexible solutions for
     cryptographic algorithms. We focus on PipeRench, a reconfigurable
     fabric that supports implementations which can yield better than
     custom-hardware performance and yet maintains all the flexibility
     of software based systems. PipeRench is a pipelined
     reconfigurable fabric which virtualizes hardware, enabling large
     circuits to be run on limited physical hardware. We present
     implementations for Crypton, IDEA, RC6, and Twofish on PipeRench
     and an extension of PipeRench, PipeRench+. We also describe how
     various proposed AES algorithms could be implemented on
     PipeRench. PipeRench achieves speedups of between 2x and 12x over
     conventional processors.},
  url = {http://www.cs.cmu.edu/~seth/papers/reed-ches99.pdf},
  keywords = {PipeRench,Reconfigurable Computing},
}

@inproceedings{goldstein-isca99,
  author = {Goldstein, Seth Copen and Schmit, Herman and Moe, Matthew
     and Budiu, Mihai and Cadambi, Srihari and Taylor, R. Reed and
     Laufer, Ronald},
  title = {{PipeRench}: a Coprocessor for Streaming Multimedia
     Acceleration},
  booktitle = {Proceedings of the 26th International Symposium on
     Computer Architecture (ISCA)},
  month = {May},
  year = {1999},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-isca99.pdf},
  pages = {28--39},
  abstract = {Future computing workloads will emphasize an
     architecture's ability to perform relatively simple calculations
     on massive quantities of mixed-width data. This paper describes a
     novel reconfigurable fabric architecture, PipeRench, optimized to
     accelerate these types of computations. PipeRench enables fast,
     robust compilers, supports forward compatibility, and virtualizes
     configurations, thus removing the fixed size constraint present
     in other fabrics. For the first time we explore how the bit-width
     of processing elements affects performance and show how the
     PipeRench architecture has been optimized to balance the needs of
     the compiler against the realities of silicon. Finally, we
     demonstrate extreme performance speedup on certain computing
     kernels (up to 190x versus a modern RISC processor), and analyze
     how this acceleration translates to application speedup.},
  address = {Atlanta, GA},
  keywords = {Reconfigurable Computing,PipeRench},
}

@inproceedings{cadambi-fccm99,
  title = {CPR: A Configuration Profiling Tool},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fccm99.pdf},
  booktitle = {7th Annual IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM '99)},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  year = {1999},
  pages = {104},
  address = {Napa Valley, CA},
  month = {Apr},
  keywords = {CAD,Reconfigurable Computing,Place And Route},
}

@inproceedings{budiu-fpga99,
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  title = {Fast Compilation for Pipelined Reconfigurable Fabrics},
  booktitle = {Proceedings of the 1999 ACM/SIGDA Seventh International
     Symposium on Field Programmable Gate Arrays (FPGA '99)},
  month = {Feb},
  year = {1999},
  pages = {195-205},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-fpga99.pdf},
  abstract = {In this paper we describe a compiler which quickly
     synthesizes high quality pipelined datapaths for pipelined
     reconfigurable devices. The compiler uses the same internal
     representation to perform synthesis, module generation,
     optimization, and place and route. The core of the compiler is a
     linear time place and route algorithm more than two orders of
     magnitude faster than traditional CAD tools. The key behind our
     approach is that we never backtrack, rip-up, or re-route.
     Instead, the graph representing the computation is preprocessed
     to guarantee routability by inserting lazy noops. The
     preprocessing steps provides enough information to make a greedy
     strategy feasible. The compilation speed is approximately 3000
     bit-operations/second (on a PII/400Mhz) for a wide range of
     applications. The hardware utilization averages 60\% on the
     target device, PipeRench.},
  keywords = {Reconfigurable Computing,PipeRench,Place and Route},
}

@inproceedings{goldstein-ymw98,
  title = {The Lazy Multithreaded Implementation Design Space},
  booktitle = {The Yale Multithreaded Workshop},
  author = {Goldstein, Seth Copen and Culler, David E.},
  address = {New Haven, CT},
  year = {1998},
  month = {Jun},
  keywords = {Lazy Threads,Parallel Computing},
}

@inproceedings{blanton-ftc98,
  author = {Blanton, Shawn and Goldstein, Seth Copen and Schmit,
     Herman},
  title = {Tunable Fault Tolernace via Test and Reconfiguration},
  booktitle = {Digest of FastAbstracts of the 28th Annual
     International Symposium on Fault-Tolerant Computing},
  year = {1998},
  month = {Jun},
  pages = {9--10},
  keywords = {PipeRench, Fault and Defect Tolerance},
  url = {http://www.cs.cmu.edu/~seth/papers/blanton-ftc98.pdf},
}

@inproceedings{moe-fccm98,
  author = {Moe, Matthew and Schmit, Herman and Goldstein, Seth
     Copen},
  title = {{Characterization and Parameterization of a Pipeline
     Reconfigurable {FGPA}}},
  booktitle = {6th Annual IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM '98)},
  month = {Apr},
  address = {Napa, CA},
  year = {1998},
  pages = {294--295},
  note = {poster session 3},
  keywords = {PipeRench, Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/moe-fccm98.pdf},
}

@inproceedings{cadambi-fpga98,
  author = {Cadambi, Srihari and Weener, J. and Goldstein, Seth Copen
     and Schmit, Herman and Thomas, Donald E},
  title = {{Managing pipeline-reconfigurable FPGAs}},
  booktitle = {Proceedings of the 1998 ACM/SIGDA Sixth International
     Symposium on Field Programmable Gate Arrays},
  year = {1998},
  month = {Feb},
  pages = {55--64},
  address = {Monterey, CA},
  abstract = {While reconfigurable computing promises to deliver
     incomparable performance, it is still a marginal technology due
     to the high cost of developing and upgrading applications.
     Hardware virtualization can be used to significantly reduce both
     these costs. In this paper we describe the benefits of hardware
     virtualization, and show how it can be acheived using a
     combination of pipeline reconfiguration and run-time scheduling
     of both configuration streams and data streams. The result is
     PipeRench, an architecture that supports robust compilation and
     provides forward compatibility. Our preliminary performance
     analysis predicts that PipeRench will outperform commercial FPGAs
     and DSPs in both overall performance and in performance per
     mm$^2$.},
  keywords = {PipeRench, Reconfigurable Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpga98.pdf},
}

@phdthesis{goldstein-phd97,
  title = {Lazy Threads Compiler and Runtime Structures for
     Fine-Grained Parallel Programming},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-phd97.pdf},
  author = {Goldstein, Seth Copen},
  school = {University of California--Berkeley},
  year = {1997},
  address = {Berkeley, CA},
  keywords = {Lazy Threads,Parallel Computing,Split-C,Threaded
     Abstract Machine (TAM)},
}

@article{ait-kaci-jlp97,
  author = {Hassan, Ait-Kaci and Podelski, Andreas and Goldstein, Seth
     Copen},
  title = {Order-sorted feature theory unification},
  journal = {The Journal of Logic Programming},
  volume = {30},
  month = {Feb},
  year = {1997},
  abstract = {Order-sorted feature (OSF) terms provide an adequate
     representation for objects as flexible records. They are sorted,
     attributed, possibly nested structures, ordered thanks to a
     subsort ordering. Sorts definitions offer the functionality of
     classes imposing structural constraints on objects. These
     constraints involve variable sorting and equations among feature
     paths, including self-reference. Formally, sort definitions may
     be seen as axioms forming an OSF theory. OSF theory unification
     is the process of normalizing an OSF term taking into account
     sort definitions, enforcing structural constraints imposed by an
     OSF theory. It allows objects to inherit, and thus abide by,
     constraints from their classes. We propose a formal system that
     logically models record objects with (possibly recursive) class
     definitions accommodating multiple inheritance. We show that OSF
     theory unification is undecidable in general. However, we give a
     set of confluent normalization rules which is complete for
     detecting the inconsistency of an object with respect to an OSF
     theory. Furthermore, a subset consisting of all rules but one is
     confluent and terminating. This yields a practical complete
     normalization strategy, as well as an effective compilation
     scheme.},
  pages = {99--124},
  number = {2},
  url = {http://www.cs.cmu.edu/~seth/papers/ait-kaci-jlp97.pdf},
  doi = {doi:10.1016/S0743-1066(96)00053-2},
  also = {Proceedings of the International Symposium on Logic
     Programming (ILPS), 1993 and as DEC Technical Report PRL-RR-32},
  keywords = {Logic Programming},
}

@article{goldstein96-jpdc,
  author = {Goldstein, Seth Copen and Schauser, Klaus Erik and Culler,
     David E.},
  title = {Lazy threads: implementing a fast parallel call},
  journal = {Journal of Parallel and Distributed Computing},
  volume = {37},
  number = {1},
  year = {1996},
  pages = {5--20},
  publisher = {Academic Press, Inc.},
  address = {Orlando, FL, USA},
  keywords = {Lazy Threads, Parallel Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein96-jpdc.pdf},
  abstract = {In this paper, we describe lazy threads, a new approach
     for implementing multithreaded execution models on conventional
     machines. We show how they can implement a parallel call at
     nearly the efficiency of a sequential call. The central idea is
     to specialize the representation of a parallel call so that it
     can execute as a parallel-ready sequential call. This allows
     excess parallelism to degrade into sequential calls with the
     attendant efficient stack management and direct transfer of
     control and data, yet a call that truly needs to execute in
     parallel, gets its own thread of control. The efficiency of lazy
     threads is achieved through a careful attention to storage
     management and a code generation strategy that allows us to
     represent potential parallel work with no overhead.},
}

@inproceedings{schauser-fplca95,
  title = {How Much Non-Strictness Do Lenient Programs Require?},
  url = {http://www.cs.cmu.edu/~seth/papers/schauser-fplca95.pdf},
  booktitle = {Conference on Functional Programming Languages and
     Computer Architecture},
  author = {Schauser, Klaus Erik and Goldstein, Seth Copen},
  address = {La Jolla, CA},
  year = {1995},
  month = {Jun},
  keywords = {Functional Programming, Parallel Computing},
}

@inproceedings{callahan-isca95,
  title = {NIFDY: A Low Overhead, High Throughput Network Interface},
  url = {http://www.cs.cmu.edu/~seth/papers/callahan-isca95.pdf},
  booktitle = {Proceedings of the 22nd International Symposium on
     Computer Architecture},
  author = {Callahan, Timothy J and Goldstein, Seth Copen},
  address = {Santa Margherita Ligure, Italy},
  year = {1995},
  month = {Jun},
  keywords = {parallel Computing, NIFDY},
}

@inproceedings{goldstein-lcr95,
  title = {Enabling Primitives for Compiling Parallel Languages},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-lcr95.pdf},
  booktitle = {Third Workshop on Languages, Compilers, and Run-Time
     Systems for Scalable Computers},
  author = {Goldstein, Seth Copen and Culler, David E. and Schauser,
     Klaus Erik},
  address = {Rochester, NY},
  year = {1995},
  month = {May},
  keywords = {Parallel Computing,Lazy Threads},
}

@techreport{dusseau-tr92,
  title = {Introduction to Split-C},
  url = {http://www.cs.cmu.edu/~seth/papers/dusseau-tr92.pdf},
  author = {Culler, David E. and Dusseau, Andrea and Goldstein, Seth
     Copen and Krishnamurthy, Arvind and Lumetta, Steven and
     von~Eicken, Thorsten and Yelick, Katherine},
  month = {Apr},
  institution = {University of California--Berkeley},
  year = {1995},
  keywords = {Parallel Computing,Split-C},
}

@techreport{GSC95,
  author = {Goldstein, Seth Copen and Culler, David E. and Schauser,
     Klaus Erik},
  title = {{Lazy Threads, Stacklets, and Synchronizers: Enabling
     primitives for compiling parallel languages}},
  institution = {University of California at Berkeley},
  year = {1995},
  keywords = {Lazy Threads, Parallel Computing},
}

@inproceedings{SCG95,
  author = {Schauser, Klaus Erik and Culler, David E. and Goldstein,
     Seth Copen},
  booktitle = {Proceedings of the Principles of Programming
     Languages},
  title = {Separation Constraint Partitioning --- A New Algorithm for
     Partitioning non-Strict Programs Into Sequential Threads},
  year = {1995},
  address = {San Francisco, CA},
  month = {Jan},
  keywords = {Parallel Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/SCG95.pdf},
}

@mastersthesis{goldstein94,
  author = {Goldstein, Seth Copen},
  title = {The Implementation of a Threaded Abstract Machine},
  school = {University of California at Berkeley},
  year = {1994},
  address = {Computer Science Division, University of California,
     Berkeley, Ca 94720},
  month = {May},
  also = {UC-Berkeley Technical Report UCB/CSD-94-818},
  keywords = {Parallel Computing, Threaded Abstract Machine (TAM)},
}

@techreport{goldstein-tr94,
  author = {Goldstein, Seth Copen},
  title = {The Implementation of a Threaded Abstract Machine},
  institution = {EECS Department, University of California, Berkeley},
  year = {1994},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-tr94.pdf},
  number = {UCB/CSD-94-818},
  see = {goldstein94},
  keywords = {Threaded Abstract Machine (TAM)},
}

@misc{goldstein-cm5users94,
  title = {Active Messages: A Communication Foundation for Parallel
     Programming Models},
  howpublished = {CM-5 Users Group},
  author = {Goldstein, Seth Copen},
  address = {Santa Fe, NM},
  year = {1994},
  month = {Feb},
  keywords = {Active Messages,Parallel Computing},
}

@article{CullerGSvE93,
  author = {Culler, David E. and Goldstein, Seth Copen and Schauser,
     Klaus Erik and von~Eicken, Thorsten},
  title = {{TAM --- a compiler controlled threaded abstract machine}},
  journal = {Journal of Parallel and Distributed Computing},
  year = {1993},
  volume = {18},
  pages = {347-370},
  month = {Jul},
  abstract = {The Threaded Abstract Machine (TAM) refines dataflow
     execution models to address the critical constraints that modern
     parallel architectures place on the compilation of
     general-purpose parallel programming languages. TAM defines a
     self-scheduled machine language of parallel threads, which
     provides a path from dataflow-graph program representations to
     conventional control flow. The most important feature of TAM is
     the way it exposes the interaction between the handling of
     asynchronous message events, the scheduling of computation, and
     the utilization of the storage hierarchy. This paper provides a
     complete description of TAM and codifies the model in terms of a
     pseudo machine language TL0. Issues in compilation from a high
     level parallel language to TL0 are discussed in general and
     specifically in regard to the Id90 language. The implementation
     of TL0 on the CM-5 multiprocessor is explained in detail. Using
     this implementation, a cost model is developed for the various
     TAM primitives. The TAM approach is evaluated on sizable Id90
     programs on a 64 processor system. The scheduling hierarchy of
     quanta and threads is shown to provide substantial locality while
     tolerating long latencies. This allows the average thread
     scheduling cost to be extremely low.},
  url = {http://www.cs.cmu.edu/~seth/papers/CullerGSvE93.pdf},
  keywords = {Active Messages, Parallel Computing,Threaded Abstract
     Machine (TAM)},
}

@inproceedings{SpertusGSvECD93,
  author = {Spertus, Ellen and Goldstein, Seth Copen and Schauser,
     Klaus Erik and von~Eicken, Thorsten and Culler, David E. and
     Dally, William J.},
  title = {{Evaluation of Mechanisms for Fine-Grained Parallel
     Programs in the J-Machine and the CM-5}},
  booktitle = {Proceedings of the 20th International Symposium on
     Computer Architecture (ISCA)},
  address = {San Diego, CA},
  month = {May},
  year = {1993},
  keywords = {Active Messages, Parallel Computing,Threaded Abstract
     Machine (TAM)},
  url = {http://www.cs.cmu.edu/~seth/papers/SpertusGSvECD93.pdf},
}

@techreport{ait-kaci-prl93,
  author = {Hassan, Ait-Kaci and Podelski, Andreas and Goldstein, Seth
     Copen},
  title = {Order-sorted feature theory unification},
  institution = {DEC Paris Research Labs},
  number = {PRL-RR-32},
  year = {1993},
  see = {ait-kaci-jlp97},
  keywords = {Logic Programming},
  url = {http://www.cs.cmu.edu/~seth/papers/ait-kaci-prl93.pdf},
}

@inproceedings{culler-sc93,
  author = {Culler, David E. and Dusseau, Andrea and Goldstein, Seth
     Copen and Krishnamurthy, Arvind and Lumetta, Steven and
     von~Eicken, Thorsten and Yelick, Katherine},
  title = {Parallel Programming in Split-C},
  booktitle = {Proceedings of the Supercomputing '93 Conference},
  pages = {262-273},
  year = {1993},
  address = {Portland, OR},
  month = {Nov},
  keywords = {Active Messages,Parallel Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/culler-sc93.pdf},
}

@inproceedings{voneicken-isca92,
  author = {von~Eicken, Thorsten and Culler, David E. and Goldstein,
     Seth Copen and Schauser, Klaus Erik},
  title = {{Active Messages}: A Mechanism for Integrated Communication
     and Computation},
  month = {May},
  booktitle = {Proceedings of the 19th International Symposium on
     Computer Architecture (ISCA)},
  address = {Gold Coast, Australia},
  pages = {430--440},
  year = {1992},
  url = {http://www.cs.cmu.edu/~seth/papers/voneicken-isca92.pdf},
  abstract = {The design challenge for large-scale multiprocessors is
     (1) to minimize communication overhead, (2) allow communication
     to overlap computation, and (3) coordinate the two without
     sacrificing processor cost/performance. We show that existing
     message passing multiprocessors have unnecessarily high
     communication costs. Research prototypes of message driven
     machines demonstrate low communication overhead, but poor
     processor cost/performance. We introduce a simple communication
     mechanism, {\em Active Messages}, show that it is intrinsic to
     both architectures, allows cost effective use of the hardware,
     and offers tremendous flexibility. Implementations on nCUBE/2 and
     CM-5 are described and evaluated using a split-phase
     shared-memory extension to C, {\em Split-C}. We further show that
     active messages are sufficient to implement the dynamically
     scheduled languages for which message driven machines were
     designed. With this mechanism, latency tolerance becomes a
     programming/compiling concern. Hardware support for active
     messages is desirable and we outline a range of enhancements to
     mainstream processors.},
  keywords = {Active Messages, Parallel Computing},
}

@inproceedings{culler-wdc92,
  author = {Culler, David E. and Goldstein, Seth Copen and Schauser,
     Klaus Erik and von~Eicken, Thorsten},
  title = {{Empirical Study of a Dataflow Language on the CM-5}},
  booktitle = {Proc. of the Dataflow Workshop, 19th Int'l Symposium on
     Computer Architecture},
  address = {Gold Coast, Australia},
  month = {May},
  year = {1992},
  pages = {187--210},
  keywords = {Parallel Computing,Threaded Abstract Machine (TAM),
     Id90, Dataflow},
  url = {http://www.cs.cmu.edu/~seth/papers/culler-wdc92.pdf},
}

@inproceedings{goldstein-ilpc92,
  title = {Supporting Implicitly Parallel Languages},
  booktitle = {14th Annual Industrial Liaison Program Conference},
  author = {Goldstein, Seth Copen},
  address = {Berkeley, CA},
  year = {1992},
  month = {Mar},
  keywords = {Parallel Computing,Threaded Abstract Machine (TAM),
     Id90},
}

@techreport{goldstein-prl92,
  author = {Goldstein, Seth Copen},
  title = {An Abstract Machine to Implement Functions in LIFE},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-prl92.pdf},
  institution = {DEC Paris Research Lab},
  year = {1992},
  number = {Note 18},
  keywords = {Logic Programming},
}

@inproceedings{goldstein-id92,
  title = {Studying Dynamic Program Behavior `In the Large'},
  booktitle = {ID Workshop},
  author = {Goldstein, Seth Copen},
  address = {Minneapolis, MN},
  year = {1992},
  month = {Nov},
  keywords = {Parallel Computing,Threaded Abstract Machine (TAM),
     Id90},
}

@inproceedings{bacon-wpdd91,
  title = {Hardware-Assisted Replay of Multiprocessor Programs},
  url = {http://www.cs.cmu.edu/~seth/papers/bacon-wpdd91.pdf},
  booktitle = {Proceedings of the ACM/ONR Workshop on Parallel and
     Distributed Debugging},
  author = {Bacon, David F. and Goldstein, Seth Copen},
  year = {1991},
  address = {Santa Cruz, CA},
  month = {May},
  keywords = {Debugging,Parallel Computing},
}

@inproceedings{goldstein-tools90,
  title = {The Future of Object-Oriented Programming},
  booktitle = {TOOLS 1990},
  author = {Goldstein, Seth Copen},
  address = {Paris, France},
  year = {1990},
  month = {May},
  keywords = {Object-Oriented Programming},
}