Mihai Budiu's Old Research Web Page

ASH

CASH

My research explores a new model of computation: ASH, Application-Specific Hardware. In this model of computation one no longer uses general-purpose processors (i.e. microprocessors) to execute programs. Instead, high-level language programs are directly compiled by CASH (Compiler for ASH) into asynchronous circuits. My work is focused on developing CASH and cycle-accurate simulations for ASH systems. CASH is described in FPL '02 and CGO '03. My defense [Powerpoint] [pdf] contains some interesting results. See also our ASYNC 2004 tutorial. My thesis describes in detail the compilation process and compares ASH with other computational substrates. I show that ASH can effectively exploit the instruction-level parallelism in media kernels. On control-intensive kernels ASH is somewhat less effective than a superscalar processor, since it lacks branch prediction and general speculation support, and incurs additional synchronization overheads. ASH is however up to three orders of magnitude more power-efficient than superscalar processors, one to two orders of magnitude better than low-power DSP processors, one order of magnitude better than asynchronous processors, and approaches custom hand-designed hardware. These results are summarized on our ASPLOS '04 paper.

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This work is part of the Phoenix research project, supervised by Seth Goldstein

PipeRench

DIL

Process: 0.18 micron 6 Al metal layers Area: 49 square mm Clock: 60MHz I/O 120MHz internal Power: < 4W Stripes: 16 physical 256 virtual

Previously I wrote the DIL compiler for the CMU Configurable Computing Project, led by Seth Goldstein and Herman Schmit. The project has developed a custom reconfigurable chip, PipeRench, and a set of CAD and compilation tools. PipeRench has been licensed by Rapport Inc., a Silicon Valley start-up, and is the basis of the commercialized Kilocore chip. PipeRench has some striking features: regularity (it is composed of many identical pipeline stages), pipeline reconfiguration (apparent reconfiguration time is one clock cycle), hardware virtualization (aparent hardware size is "infinite"), datapath orientation (8-bit computational units), extremely fast compilation of a high-level language (DIL), including place and route (comparable to gcc). For more information, take a look at the slides [ps] [ppt] from an April 1999 talk I gave about PipeRench. The canonical PipeRench paper is from ISCA '99.

Selected Research Publications

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