Proposal
http://www.cs.cmu.edu/~uhengart/15-740
Rajesh Krishna Balan and Urs Hengartner
{rajesh, uhengart}@cs.cmu.edu
Network processing in routers so far has mainly relied on either custom-built network ASICs or general-purpose processors. The first approach has the benefit of being able to achieve high performance, on the other hand, it is difficult to extend an ASIC to make it support new protocols. The second approach is easily extendable, but it may suffer in terms of performance. Recently, programmable network processors started to appear which try to unify the positive aspects of both worlds. Programmable network processors typically consist of an embedded control processor and several data processing engines. The control processor is responsible for executing the control plane functionality of a router (e.g., maintenance of the routing table), whereas data-plane (per packet) operations (e.g,. packet classification) are performed by the data processing engines. An example of such a network processor is the Intel IXP1200 Network Processor1.
The IXP1200 consists of a StrongARM core and six programmable microengines. The core runs the VxWorks operating system and schedules the microengine threads. Each microengine can execute up to four threads and its instruction set is specially designed for packet processing. An instruction is piped through a five-stage pipeline with the execution stage taking one cycle for each instruction.
In our project, we are going to evaluate the IXP1200 Network Processor.
Our performance analysis is based on a simulator of the IXP1200. We will evaluate the processor using one or multiple of the example applications (e.g., IP routing) included in the development environment. The simulator provides high-level statistics and per pipeline stage output for the microengines. To get fine-grained information such as average instructions in flight or number of branch mispredictions, we will write scripts to process this output. We are also interested in metrics like memory bandwidth and packet throughput. Finally, we will try to find bottlenecks and to propose workarounds for them.
Although we have access to evaluation systems of the IXP1200, our performance analysis will be mainly based on a simulator of this processor. The simulator runs on Windows NT and its source code is not available. We already have the software and machines to run it on.
Programmable network processors are currently of big interest in the networking community. This observation is emphasized by the fact that several startups announcing solutions in this area have been bought by big players (e.g,. Level One by Intel or Agere by Lucent). Unfortunately, since this kind of processors has begun to show up only recently, there is still a lack of commonly accepted benchmarks or detailed evaluations. In our work, we will thus refrain to evaluations of conventional processors (such as Cvetanovic and Kessler's performance analysis of the Alpha 21264 [1]) to learn more about methodology-related issues.
The schedule for our work is given below. The writing and the evaluation part will be appropriately shared between the group members.
| Date | Milestone |
| Oct 23 | Become familiar with the IXP1200 |
| Oct 30 | Become familiar with the simulator and the applications |
| Nov 6 | Figure out metrics for evaluation |
| Nov 13 | Write scripts for analysis |
| Nov 20 | Get preliminary evaluation results |
| Nov 27 | Finish evaluation |
| Dec 4 | Write project report |
By Nov 20, we will have preliminary evaluation results. We have already started looking at the IXP1200.