Basic Architectural Support for Prefetching

Chapters and assumed a ``base'' model for prefetching, including a prefetch instruction, lockup-free caches, etc. In this section, we will examine that model in more detail and discuss some important tradeoffs. We begin in Section by discussing key properties of prefetch instructions and how to incorporate them into a processor's instruction set architecture. Given that prefetches are performance hints, and therefore can be dropped, in Section we evaluate when it is appropriate to drop prefetches. In Section we discuss how prefetches that are not dropped should proceed through the memory hierarchy, and where the resulting data should be placed (e.g., should it go directly into the primary cache). We conclude in Section by discussing the more significant hardware modifications needed to support prefetching, such as providing lockup-free caches.

• Instruction Set Architecture
  • Behavioral Properties
  • Format
  • Encoding
• Dropping Prefetches
  • TLB Miss
  • Full Prefetch Issue Buffer
  • Summary
• Performing the Prefetch Memory Access
  • Checking Caches While Searching for the Data
  • Prefetching into the Primary Data Cache
  • Prefetching into a Separate Prefetch Target Buffer
• Hardware Modifications to Support Prefetching
  • Lockup-Free Cache
  • Separate Write and Prefetch Issue Buffers
  • Summary