Michael K. Papamichael        
 

 
  
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Intel
2012		 Michael K. Papamichael, James C. Hoe. "CONNECT: Fast Flexible FPGA-Tuned Networks-on-Chip", Intel PhD Fellowship Forum 2012, Hillsboro, OR, August 19-21, 2012
NOCS
2011		 Michael K. Papamichael, James C. Hoe, Onur Mutlu. "FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations", 5th ACM/IEEE International Symposium on Networks on Chip, Pittsburgh, PA, May 3, 2011
Ramp Retreat
2010		 Eric S. Chung, Michael K. Papamichael, James C. Hoe, Babak Falsafi, Ken Mai. "The Open-Source ProtoFlex Simulator", RAMP Retreat, Santa Cruz, CA, USA, January 29, 2010 View poster online
Ramp Retreat
2008		 Michael K. Papamichael, Eric S. Chung, James C. Hoe, Babak Falsafi, Ken Mai. "Protoflex: Complexity-Effective FPGA-Accelerated Instrumentation", RAMP Retreat, Stanford University, Palo Alto, CA, USA, August 19, 2008 View poster online
ASPLOS
2008		 Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai. "An MP Architectural Exploration Vehicle Using Complexity-Effective FPGA-Accelerated Simulation", ASPLOS XIII, Seattle, WA, USA, March 2, 2008 View poster online
Ramp Retreat
2008		 Michael K. Papamichael, Wei Yu, Yongjun Jeon. "Protoflex: Complexity-Effective FPGA-Accelerated Instrumentation", RAMP Retreat, Universtiy of California, Berkeley, CA, USA, January 16, 2008
ACACES
2007		 V. Papaefstathiou and M. Papamichael (in collaboration with S. Kavadias, G. Kalokairinos, D. Pnevmatikatos and M. Katevenis). "Interprocessor Communication: Towards Cache Integrated Network Interfaces", Poster presented at the 3rd HiPEAC Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2007), 15-20 July 2007, L' Aquila, Italy. [abstract]
OCIN
2006		 V. Papaefstathiou, G. Kalokairinos, A. Ioannou, M. Papamichael, G. Mihelogiannakis, S. Kavadias, E. Vlahos, D. Pnevmatikatos and M. Katevenis. "An FPGA-based Prototyping Platform for Research in High-Speed Interprocessor Communication", Poster presented at the 2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN2006), 6-7 December 2006, Stanford California, USA.