Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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Bevan M. Baas	Professor UC Davis ECE ece.ucdavis.edu/~bbaas/		processor architecture, VLSI design, fast Fourier transform processors, low power CMOS
John Backus	computerhistory.org/events/hall_of_fellows/backus/ Turing (1977) award		FORTRAN, Backus-Naur form dblp
David F. Bacon	Researcher IBM T. J. Watson research.ibm.com/people/d/dfb/		design and implementation of programming languages, concurrent systems dblp
Wael M. Badawy	Professor U of Calgary, Canada badawy.ca		architectures for image and video processing, system on a chip dblp
Scott B. Baden	Professor UC San Diego, CS cs.ucsd.edu/users/baden		high performance and scientific computation, application-specific programming models and optimization strategies, KeLP dblp
Jean-Loup Baer	Professor U of Washington Seattle, CS cs.washington.edu/homes/baer		caches, computer architecture, programmable network interfaces dblp
Nader Bagherzadeh	Professor UC Irvine eng.uci.edu/comp.arch/nader.html		MorphoSys, multithreaded architectures, processor architecture dblp
R. Iris Bahar	Professor Brown U, ECE lems.brown.edu/iris.html		computer architecture, low-power design, CAD, nanosystem design dblp
Vasanth Bala	IBM research		parallel computation, Dynamo, dynamic optimization dblp
Thomas Ball	Microsoft Research, Software Productivity Tools research.microsoft.com/~tball		formal methods for programs dblp
Prithviraj Banerjee	Professor Northwestern U, ECE ece.nwu.edu/~banerjee		parallel algorithms for VLSI design automation, distributed memory parallel compilers, compilers for adaptive computing, PARADIGM, ProperCAD, MATCH dblp
Cristina Barrado	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/cristina		automatic parallelization dblp
Luiz André Barroso	Google barroso.org		server workloads, SimOS-Alpha dblp
Rajeev Barua	Professor U of Maryland, ECE ece.umd.edu/~barua		MAPS (Raw compiler), modulo unrolling dblp
Forest Baskett	Venture Partner New Enterprise Associates nea.com/Partners/Bios/Menlo/FBaskettBio		MIPS, SUN, DEC WRL founder dblp
Kenneth E. Batcher	Professor Kent State U, CS cs.kent.edu/~batcher Eckert-Mauchly (1990) award		parallel computers, interconnection networks dblp
Jürgen Becker	Professor U of Karslruhe www-itiv.etec.uni-karlsruhe.de/opencms/opencms/de/institute/staff/becker.html		hardware/software codesign, hardware synthesis, systems-on-a-chip dblp
Robert C. Bedichek	Transmeta Corp. bedichek.org/robert		Alewife, Meerkat, multicomputers dblp
Peter A. Beerel	Professor U of Southern California jungfrau.usc.edu/beerel.html		CAD, mixed asynchronous/synchronous VLSI design dblp
Richard A. Belgard	Consultant members.aol.com/richb89600		computer architecture
Gordon Bell	senior researcher Microsoft Bay Area Research Center research.microsoft.com/users/GBell Eckert-Mauchly (1982) award		minicomputers, timeshring, hardware description languages dblp
Luca Benini	Professor U of Bologna, Italy www-micrel.deis.unibo.it/~benini		computer-aided design of digital circuits, low-power applications, design of portable systems dblp
Siegfried Benkner	Professor U of Vienna, Austria par.univie.ac.at/~sigi		ADVANCE, AURORA, HPF+ dblp
Steve Bennett	Intel, Hillsboro intel.com/research/people/bios/bennett_s.htm		SimpleScalar, trace cache, multiscalar dblp
Alan D. Berenbaum	Agere Systems cm.bell-labs.com/cm/cs/who/adb		computer architecture, architectural support for high-speed networking, VLSI design dblp
Emery D. Berger	Professor U of Massachusetts Amherst, CS cs.umass.edu/~emery		garbage collection, virtual memory management, locality-preserving data structures, compilers for high-level optimization and error detection dblp
Neil W. Bergmann	Professor U of Queensland, Brisbane, Australia itee.uq.edu.au/~bergmann		reconfigurable computing, embedded systems infrastructure for ubiquitous computing dblp
Kees van Berkel	Philips Research, Netherlands research.philips.com/profile/people/fellows/berkel.html		asynchronous circuits, VLSI design dblp
David Bernstein	Department Manager Systems and Software, IBM Research Israel		code scheduling, optimizing compilers dblp
Gerard Berry	Professor Ecole des Mines, Paris, France www-sop.inria.fr/meije/personnel/Gerard.Berry.html		programming languages design/semantics/implementation, reactive and real-time programming, synchronous circuit design and synthesis, automatic verification of FSM, lambda calculus and its models dblp
Vaughn Betz	Altera Corp. eecg.toronto.edu/~vaughn (old)		FPGAs, CAD for FPGAS, computer architecture, VLSI design, VPR dblp
Dileep Bhandarkar	Director of Enterprise Architecture Lab Intel intel.com/pressroom/kits/bios/dbhandarkar.htm		VAX, Prism, MIPS, Alpha, memories, computer architecture dblp
Shuvra S. Bhattacharyya	Professor U of Maryland, ECE ece.umd.edu/~ssb		architectures and CAD for embedded systems, hardware/software co-design for signal/image/video processing dblp
Laxmi N. Bhuyan	Professor UC Riverside, CS cs.ucr.edu/~bhuyan		computer architecture, performance evaluation, parallel and distributed systems, interconnection networks, fault tolerant computing dblp
Ricardo Bianchini	Professor Rutgers U, CS cs.rutgers.edu/~ricardob		parallel/distributed and cluster computing, techniques for optimizing power and energy, new I/O architectures, Internet-related technologies dblp
Armin Biere	Professor ETH Zurich, Switzerland inf.ethz.ch/personal/biere		model checking, hardware verification dblp
Aart J. C. Bik	Intel liacs.nl/home/ajcbik		compilers for scientific computing, Java compilation, automatic vectorization dblp
Angelos Bilas	Professor U of Crete, Greece wwww.ics.forth.gr/~bilas		parallel architectures, programming paradigms, parallel applications, interconnection networks, block-level storage subsystems, performance analysis and evaluation, distributed systems dblp
Benjamin J. Bishop	Professor U of Scranton, CS cs.uofs.edu/~bishop		multimedia systems, computer graphics, processor architecture, VLSI design, low-power electronics, MGAP-II, SPARTA dblp
David T. Blaauw	Professor U of Michigan at Ann Arbor eecs.umich.edu/cgi-bin/fac/facsearchform.cgi?blaauw+		circuit analysis, computer-aided design, high performance design dblp
Stephen M. Blackburn	Professor Australian National U, Australia cs.anu.edu.au/~Steve.Blackburn		programming languages, dynamic cooperative performance optimization Java, transactional object storage, image processing dblp
R. D. (Shawn) Blanton	Professor Carnegie Mellon U, ECE ece.cmu.edu/~blanton		design and test of VLSI, fault-tolerant computing, computer architecture dblp
Guy E. Blelloch	Professor Carnegie Mellon U, CS cs.cmu.edu/~guyb		thread scheduling, parallel algorithms, NESL language, parallel computing dblp
Matthias Blume	Professor Toyota Technical Institute, Chicago people.cs.uchicago.edu/~blume		design and implementation of high-level programming languages, SML/NJ dblp
Matthias A. Blumrich	IBM Research cs.princeton.edu/~mb (old)		SHRIMP, shared memory multiprocessing dblp
Arndt Bode	Professor Technische U Muenchen, Germany wwwbode.cs.tum.edu/~bode		parallel and distributed architectures/applications, programming environments and tools dblp
Rastislav Bodík	Professor UC Berkeley cs.berkeley.edu/~bodik		critical path, compilers, computer architecture dblp
François Bodin	Researcher IRISA, France irisa.fr/caps/people/bodin/index_fr.htm		program optimizations, HPC programming environments, compilers, ILP, parallel computers dblp
Hans-Juergen Boehm	Hewlett-Packard Labs hpl.hp.com/personal/Hans_Boehm/		Boehm-Weiser garbage collector, gcj, multiprocessor synchronization, constructive real arithmetic dblp
Taisuke Boku	Professor U of Tsukuba, Japan arch.is.tsukuba.ac.jp/~taisuke/index-e.html		network topology, data transfer methods for HPC on MPPs dblp
Shekhar Y. Borkar	Director of Circuit Research Intel intel.com/research/people/bios/borkar_s.htm		8051 microcontrollers, iWarp, high-speed signaling for supercomputers dblp
Pradip Bose	Research Staff Member IBM T. J. Watson research.ibm.com/people/b/bose		high-performance computer architectures, CAD, performance evaluation, performance verification, parallel processing, compilers, VLSI testing and verification dblp
Luc Bougé	Professor IRISA/ENS Cachan, Bretagne, France ens-lyon.fr/~bouge		semantics of languages for parallel programming, cluster computing dblp
Donald W. Bouldin	Professor U of Tennessee at Knoxville microsys6.engr.utk.edu/ece/bouldin_home.html		microelectronic systems design, adaptive computing systems, VLSI, ASICs, FPGAs, MCMs, synthesis dblp
Chandrasekhar Boyapati	Professor U of Michigan eecs.umich.edu/~bchandra		software reliability, program analysis dblp
Robert S. Boyer	Professor U of Texas, Austin, CS cs.utexas.edu/users/boyer		theorem prooving, Maxima (Macsyma clone), Boyer-Moore theorem prover, hardware verification dblp
Robert K. Brayton	Professor UC Berkeley, EE www-cad.eecs.berkeley.edu/~brayton		analysis of nonlinear networks, electrical simulation and optimization of circuits, combinational and sequential logic synthesis, asynchronous synthesis, formal verification dblp
Scott E. Breach	Hewlett-Packard cs.wisc.edu/~breach (old)		multiscalar processors dblp
Gordon J. Brebner	Professor U of Edinburgh, UK dcs.ed.ac.uk/home/gordon		flexible architecture and networking dblp
Mauricio Breternitz Jr.	Intel MRL intel.com/research/people/bios/breternitz_m.htm		parallelizing compilers multiprocessors and VLIW, binary translation, on IP telephony, parallelizing database servers dblp
Melvin A. Breuer	Professor U of Southern California poisson.usc.edu/Breuer.html		CAD, design-for-test and built-in self-test, VLSI circuits dblp
Faye A. Briggs	director of chipset architecture Intel Enterprise Products Group		computer architecture, parallel processing dblp
Robert W. Brodersen	Professor UC Berkeley, ECE bwrc.eecs.berkeley.edu/People/Faculty/rb		low power design, wireless communications, CAD tools dblp
Stephen D. Brookes	Professor Carnegie Mellon U, CS csd.cs.cmu.edu/research/faculty_research/brookes.html		semantics of programming languages, trace semantics dblp
David Brooks	Professor Harvard U eecs.harvard.edu/~dbrooks		interaction architecture/software/hardware, power dissipation and chip cooling modelling, Wattch dblp
Frederick P. Brooks Jr.	Professor U of North Carolina, CS cs.unc.edu/~brooks Turing (1999) award, von Neumann medal (1993), National Medal of Technology (1985), Allen Newell (1994) award, Eckert-Mauchly (2004) award		3D interactive computer graphics, human-computer interaction, virtual worlds, molecular graphics, IBM S/360, STRETCH, The Mythical Man-Month dblp
Mats Brorsson	Professor Royal Institute of Technology, Stockholm, Sweden it.kth.se/~matsbror		energy aware architectures, shared address space multiprocessors, programming models for parallel programs, software DSM dblp
Angela Demke Brown	Professor U of Toronto, CS, Canada cs.toronto.edu/~demke		compiler-guided resource management, run-time adaptation, operating systems, compiler optimization, parallel and distributed systems dblp
Donna J. Brown	Professor U of Illinois at Urbana-Champaign, ECE wocket.csl.uiuc.edu/~djb		VLSI layout, combinatorial algorithms, parallel and distributed algorithms and architecture, Web-based instruction, Mallard dblp
Richard B. Brown	Dean, College of Engineering U of Utah coe.utah.edu/brown		IC design (VLSI), solid-state chemical sensors, MEMS, mixed-signal circuits, high-performance, radiation-hard and low-power microprocessors, CMOS/SOI/GaAs dblp
Stephen Dean Brown	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~brown		FPGAs, CAD, place and route dblp
Erik Brunvand	Professor U of Utah, CS cs.utah.edu/~elb/home.html		computer architecture, VLSI systems, self-timed and asynchronous systems dblp
Randal E. Bryant	Professor Carnegie Mellon U, CS cs.cmu.edu/~bryant		Binary Decision Diagrams (BDD), formal verification, model checking dblp
Mihai Budiu	Microsoft Research cs.cmu.edu/~mihaib (old)		reconfigurable hardware, optimizing compilers, spatial computation dblp
Duncan A. Buell	Professor U of South Carolina cse.sc.edu/~buell		Splash 2 reconfigurable system, numeric computations, parallel algorithms and architectures, computational number theory dblp
Doug Burger	Professor U of Texas, Austin, CS cs.utexas.edu/users/dburger		SimpleScalar, Datascalar, memory systems dblp
Neil Burgess	Professor Cardiff U, UK engin.cf.ac.uk/whoswho/profile.asp?RecordNo=138		computer arithmetic, digital signal processing, hardware support for DSP dblp
Wayne P. Burleson	Professor U of Massachusetts Amherst ECE ecs.umass.edu/ece/vspgroup/burleson.html		VLSI signal processing, on-chip interconnects, reconfigurable computing dblp
Martin Burtscher	Professor Cornell U, ECE csl.cornell.edu/~burtscher		high-performance microprocessor architecture, ILP, compiler optimizations, value prediction, data compression, latency-reduction techniques dblp
Rajkumar Buyya	Professor Monash U, Australia buyya.com		computer architecture, operating systems, compilers, parallel / distributed / cluster / grid / peer-to-peer computing dblp